disp 143 arch/arm/mach-mmp/pxa910.c PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec); disp 57 arch/arm/probes/decode-arm.c int disp = branch_displacement(insn); disp 62 arch/arm/probes/decode-arm.c regs->ARM_pc = iaddr + 8 + disp; disp 69 arch/arm/probes/decode-arm.c int disp = branch_displacement(insn); disp 72 arch/arm/probes/decode-arm.c regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); disp 107 arch/arm64/kernel/probes/simulate-insn.c int disp = bbl_displacement(opcode); disp 113 arch/arm64/kernel/probes/simulate-insn.c instruction_pointer_set(regs, addr + disp); disp 119 arch/arm64/kernel/probes/simulate-insn.c int disp = 4; disp 122 arch/arm64/kernel/probes/simulate-insn.c disp = bcond_displacement(opcode); disp 124 arch/arm64/kernel/probes/simulate-insn.c instruction_pointer_set(regs, addr + disp); disp 143 arch/arm64/kernel/probes/simulate-insn.c int disp = 4; disp 147 arch/arm64/kernel/probes/simulate-insn.c disp = cbz_displacement(opcode); disp 150 arch/arm64/kernel/probes/simulate-insn.c disp = cbz_displacement(opcode); disp 152 arch/arm64/kernel/probes/simulate-insn.c instruction_pointer_set(regs, addr + disp); disp 158 arch/arm64/kernel/probes/simulate-insn.c int disp = 4; disp 162 arch/arm64/kernel/probes/simulate-insn.c disp = tbz_displacement(opcode); disp 165 arch/arm64/kernel/probes/simulate-insn.c disp = tbz_displacement(opcode); disp 167 arch/arm64/kernel/probes/simulate-insn.c instruction_pointer_set(regs, addr + disp); disp 175 arch/arm64/kernel/probes/simulate-insn.c int disp; disp 177 arch/arm64/kernel/probes/simulate-insn.c disp = ldr_displacement(opcode); disp 178 arch/arm64/kernel/probes/simulate-insn.c load_addr = (u64 *) (addr + disp); disp 193 arch/arm64/kernel/probes/simulate-insn.c int disp; disp 195 arch/arm64/kernel/probes/simulate-insn.c disp = ldr_displacement(opcode); disp 196 arch/arm64/kernel/probes/simulate-insn.c load_addr = (s32 *) (addr + disp); disp 32 arch/parisc/include/asm/pdc.h int pdc_chassis_disp(unsigned long disp); disp 302 arch/parisc/kernel/firmware.c int pdc_chassis_disp(unsigned long disp) disp 308 arch/parisc/kernel/firmware.c retval = mem_pdc_call(PDC_CHASSIS, PDC_CHASSIS_DISP, disp); disp 288 arch/powerpc/platforms/pseries/lpar.c struct vcpu_dispatch_data *disp; disp 291 arch/powerpc/platforms/pseries/lpar.c disp = this_cpu_ptr(&vcpu_disp_data); disp 292 arch/powerpc/platforms/pseries/lpar.c if (disp->last_disp_cpu == -1) { disp 293 arch/powerpc/platforms/pseries/lpar.c disp->last_disp_cpu = disp_cpu; disp 297 arch/powerpc/platforms/pseries/lpar.c disp->total_disp++; disp 299 arch/powerpc/platforms/pseries/lpar.c if (disp->last_disp_cpu == disp_cpu || disp 300 arch/powerpc/platforms/pseries/lpar.c (cpu_first_thread_sibling(disp->last_disp_cpu) == disp 302 arch/powerpc/platforms/pseries/lpar.c disp->same_cpu_disp++; disp 304 arch/powerpc/platforms/pseries/lpar.c distance = cpu_relative_dispatch_distance(disp->last_disp_cpu, disp 312 arch/powerpc/platforms/pseries/lpar.c disp->same_chip_disp++; disp 315 arch/powerpc/platforms/pseries/lpar.c disp->diff_chip_disp++; disp 318 arch/powerpc/platforms/pseries/lpar.c disp->far_chip_disp++; disp 323 arch/powerpc/platforms/pseries/lpar.c disp->last_disp_cpu, disp 337 arch/powerpc/platforms/pseries/lpar.c disp->numa_home_disp++; disp 340 arch/powerpc/platforms/pseries/lpar.c disp->numa_remote_disp++; disp 343 arch/powerpc/platforms/pseries/lpar.c disp->numa_far_disp++; disp 353 arch/powerpc/platforms/pseries/lpar.c disp->last_disp_cpu = disp_cpu; disp 500 arch/powerpc/platforms/pseries/lpar.c struct vcpu_dispatch_data *disp; disp 529 arch/powerpc/platforms/pseries/lpar.c disp = per_cpu_ptr(&vcpu_disp_data, cpu); disp 530 arch/powerpc/platforms/pseries/lpar.c memset(disp, 0, sizeof(*disp)); disp 531 arch/powerpc/platforms/pseries/lpar.c disp->last_disp_cpu = -1; disp 556 arch/powerpc/platforms/pseries/lpar.c struct vcpu_dispatch_data *disp; disp 564 arch/powerpc/platforms/pseries/lpar.c disp = per_cpu_ptr(&vcpu_disp_data, cpu); disp 566 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->total_disp); disp 567 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->same_cpu_disp); disp 568 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->same_chip_disp); disp 569 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->diff_chip_disp); disp 570 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->far_chip_disp); disp 571 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->numa_home_disp); disp 572 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->numa_remote_disp); disp 573 arch/powerpc/platforms/pseries/lpar.c seq_put_decimal_ull(p, " ", disp->numa_far_disp); disp 46 arch/s390/include/asm/ftrace.h s32 disp; disp 55 arch/s390/include/asm/ftrace.h insn->disp = 0; disp 59 arch/s390/include/asm/ftrace.h insn->disp = MCOUNT_INSN_SIZE / 2; disp 68 arch/s390/include/asm/ftrace.h if (insn->disp == 0) disp 71 arch/s390/include/asm/ftrace.h if (insn->disp == MCOUNT_INSN_SIZE / 2) disp 87 arch/s390/include/asm/ftrace.h insn->disp = (target - ip) / 2; disp 92 arch/s390/include/asm/nospec-insn.h .macro __DECODE_DRR expand,disp,reg,ruse disp 129 arch/s390/include/asm/nospec-insn.h .macro __THUNK_EX_BC disp,reg,ruse disp 147 arch/s390/include/asm/nospec-insn.h .macro GEN_B_THUNK disp,reg,ruse=%r1 disp 160 arch/s390/include/asm/nospec-insn.h .macro B_EX disp,reg,ruse=%r1 disp 178 arch/s390/include/asm/nospec-insn.h .macro GEN_B_THUNK disp,reg,ruse=%r1 disp 185 arch/s390/include/asm/nospec-insn.h .macro B_EX disp,reg,ruse=%r1 disp 261 arch/s390/include/asm/vx-insn.h .macro VLVG v, gr, disp, m disp 292 arch/s390/include/asm/vx-insn.h .macro VL v, disp, index="%r0", base disp 302 arch/s390/include/asm/vx-insn.h .macro VLEx vr1, disp, index="%r0", base, m3, opc disp 310 arch/s390/include/asm/vx-insn.h .macro VLEB vr1, disp, index="%r0", base, m3 disp 313 arch/s390/include/asm/vx-insn.h .macro VLEH vr1, disp, index="%r0", base, m3 disp 316 arch/s390/include/asm/vx-insn.h .macro VLEF vr1, disp, index="%r0", base, m3 disp 319 arch/s390/include/asm/vx-insn.h .macro VLEG vr1, disp, index="%r0", base, m3 disp 344 arch/s390/include/asm/vx-insn.h .macro VLGV gr, vr, disp, base="%r0", m disp 352 arch/s390/include/asm/vx-insn.h .macro VLGVB gr, vr, disp, base="%r0" disp 355 arch/s390/include/asm/vx-insn.h .macro VLGVH gr, vr, disp, base="%r0" disp 358 arch/s390/include/asm/vx-insn.h .macro VLGVF gr, vr, disp, base="%r0" disp 361 arch/s390/include/asm/vx-insn.h .macro VLGVG gr, vr, disp, base="%r0" disp 366 arch/s390/include/asm/vx-insn.h .macro VLM vfrom, vto, disp, base, hint=3 disp 376 arch/s390/include/asm/vx-insn.h .macro VSTM vfrom, vto, disp, base, hint=3 disp 21 arch/s390/kernel/alternative.c s32 disp; disp 67 arch/s390/kernel/ftrace.c insn->disp = 0; disp 71 arch/s390/kernel/ftrace.c insn->disp = 0xf0080024; disp 88 arch/s390/kernel/ftrace.c insn->disp = KPROBE_ON_FTRACE_NOP; disp 96 arch/s390/kernel/ftrace.c insn->disp = KPROBE_ON_FTRACE_CALL; disp 60 arch/s390/kernel/kprobes.c s64 disp, new_disp; disp 84 arch/s390/kernel/kprobes.c disp = *(s32 *)&p->ainsn.insn[1]; disp 87 arch/s390/kernel/kprobes.c new_disp = ((addr + (disp * 2)) - new_addr) / 2; disp 164 arch/s390/kernel/kprobes.c new_insn.disp = KPROBE_ON_FTRACE_NOP; disp 166 arch/s390/kernel/kprobes.c new_insn.disp = KPROBE_ON_FTRACE_CALL; disp 169 arch/s390/kernel/kprobes.c if (insn->disp == KPROBE_ON_FTRACE_NOP) disp 479 arch/s390/kernel/kprobes.c if (insn->disp == KPROBE_ON_FTRACE_CALL) { disp 480 arch/s390/kernel/kprobes.c ip += call_insn.disp * 2 - MCOUNT_INSN_SIZE; disp 234 arch/s390/kernel/uprobes.c s32 disp; disp 279 arch/s390/kernel/uprobes.c uptr = (void *)(regs->psw.addr + (insn->disp * 2)); disp 482 arch/s390/kvm/guestdbg.c u32 disp = opcode[1] & 0x0fff; disp 487 arch/s390/kvm/guestdbg.c *addr += disp; disp 168 arch/s390/net/bpf_jit_comp.c #define _EMIT4_DISP(op, disp) \ disp 170 arch/s390/net/bpf_jit_comp.c unsigned int __disp = (disp) & 0xfff; \ disp 174 arch/s390/net/bpf_jit_comp.c #define EMIT4_DISP(op, b1, b2, disp) \ disp 177 arch/s390/net/bpf_jit_comp.c reg_high(b2) << 8, disp); \ disp 204 arch/s390/net/bpf_jit_comp.c #define _EMIT6_DISP(op1, op2, disp) \ disp 206 arch/s390/net/bpf_jit_comp.c unsigned int __disp = (disp) & 0xfff; \ disp 210 arch/s390/net/bpf_jit_comp.c #define _EMIT6_DISP_LH(op1, op2, disp) \ disp 212 arch/s390/net/bpf_jit_comp.c u32 _disp = (u32) disp; \ disp 218 arch/s390/net/bpf_jit_comp.c #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ disp 221 arch/s390/net/bpf_jit_comp.c reg_high(b3) << 8, op2, disp); \ disp 79 arch/sh/kernel/cpu/sh5/unwind.c u8 src, dest, disp; disp 86 arch/sh/kernel/cpu/sh5/unwind.c disp = (op >> 10) & 0x3f; disp 109 arch/sh/kernel/cpu/sh5/unwind.c if (src == 15 && disp == 63 && dest == 14) disp 118 arch/sh/kernel/cpu/sh5/unwind.c fp_displacement -= regcache[disp]; disp 160 arch/sh/kernel/kprobes.c unsigned long disp = (p->opcode & 0x0FFF); disp 162 arch/sh/kernel/kprobes.c (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); disp 174 arch/sh/kernel/kprobes.c unsigned long disp = (p->opcode & 0x00FF); disp 179 arch/sh/kernel/kprobes.c (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); disp 184 arch/sh/kernel/kprobes.c unsigned long disp = (p->opcode & 0x00FF); disp 189 arch/sh/kernel/kprobes.c (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); disp 366 arch/x86/kernel/kprobes/core.c u8 *disp; disp 385 arch/x86/kernel/kprobes/core.c disp = (u8 *) dest + insn_offset_displacement(insn); disp 386 arch/x86/kernel/kprobes/core.c *(s32 *) disp = (s32) newdisp; disp 607 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_display *disp = nv04_display(crtc->dev); disp 614 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) disp 615 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); disp 616 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); disp 743 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_display *disp = nv04_display(crtc->dev); disp 751 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) disp 752 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); disp 753 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); disp 787 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_display *disp = nv04_display(crtc->dev); disp 789 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) disp 790 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); disp 791 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); disp 39 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nv04_display *disp = nv04_display(dev); disp 43 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_notify_put(&disp->flip); disp 77 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nv04_display *disp = nv04_display(dev); disp 100 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_notify_get(&disp->flip); disp 165 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nv04_display *disp = nv04_display(dev); disp 179 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_notify_fini(&disp->flip); disp 182 drivers/gpu/drm/nouveau/dispnv04/disp.c kfree(disp); disp 197 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nv04_display *disp; disp 200 drivers/gpu/drm/nouveau/dispnv04/disp.c disp = kzalloc(sizeof(*disp), GFP_KERNEL); disp 201 drivers/gpu/drm/nouveau/dispnv04/disp.c if (!disp) disp 206 drivers/gpu/drm/nouveau/dispnv04/disp.c nouveau_display(dev)->priv = disp; disp 218 drivers/gpu/drm/nouveau/dispnv04/disp.c NULL, 0, 0, &disp->flip); disp 43 drivers/gpu/drm/nouveau/dispnv50/base.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 46 drivers/gpu/drm/nouveau/dispnv50/base.c cid = nvif_mclass(&disp->disp->object, bases); disp 265 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 275 drivers/gpu/drm/nouveau/dispnv50/base507c.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, disp 277 drivers/gpu/drm/nouveau/dispnv50/base507c.c disp->sync->bo.offset, &wndw->wndw); disp 61 drivers/gpu/drm/nouveau/dispnv50/core.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 64 drivers/gpu/drm/nouveau/dispnv50/core.c cid = nvif_mclass(&disp->disp->object, cores); disp 92 drivers/gpu/drm/nouveau/dispnv50/core507d.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 100 drivers/gpu/drm/nouveau/dispnv50/core507d.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, disp 102 drivers/gpu/drm/nouveau/dispnv50/core507d.c disp->sync->bo.offset, &core->chan); disp 43 drivers/gpu/drm/nouveau/dispnv50/curs.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 46 drivers/gpu/drm/nouveau/dispnv50/curs.c cid = nvif_mclass(&disp->disp->object, curses); disp 116 drivers/gpu/drm/nouveau/dispnv50/curs507a.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 126 drivers/gpu/drm/nouveau/dispnv50/curs507a.c ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, disp 81 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, disp 90 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = n = nvif_object_sclass_get(disp, &sclass); disp 97 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_object_init(disp, 0, oclass[0], disp 134 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, disp 165 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_chan_create(device, disp, oclass, head, data, size, disp 262 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); disp 272 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); disp 281 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 293 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); disp 406 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 422 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); disp 486 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 498 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); disp 507 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 528 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &args, disp 539 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 551 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); disp 560 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 628 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &args, size); disp 768 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); disp 1249 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvif_object *disp = &drm->display->disp.object; disp 1270 drivers/gpu/drm/nouveau/dispnv50/disp.c return nvif_mthd(disp, 0, &args, sizeof(args)); disp 1410 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); disp 1411 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_core *core = disp->core; disp 1470 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 1531 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); disp 1610 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(encoder->dev); disp 1614 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass < GF110_DISP) { disp 1778 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 1779 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_core *core = disp->core; disp 1793 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); disp 1795 drivers/gpu/drm/nouveau/dispnv50/disp.c if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, disp 1796 drivers/gpu/drm/nouveau/dispnv50/disp.c disp->core->chan.base.device)) disp 1833 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(dev); disp 1845 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_lock(&disp->mutex); disp 1977 drivers/gpu/drm/nouveau/dispnv50/disp.c disp->core->func->update(disp->core, interlock, false); disp 1981 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_unlock(&disp->mutex); disp 2303 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(dev); disp 2305 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_core_del(&disp->core); disp 2307 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_bo_unmap(disp->sync); disp 2308 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->sync) disp 2309 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_bo_unpin(disp->sync); disp 2310 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_bo_ref(NULL, &disp->sync); disp 2313 drivers/gpu/drm/nouveau/dispnv50/disp.c kfree(disp); disp 2323 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp; disp 2327 drivers/gpu/drm/nouveau/dispnv50/disp.c disp = kzalloc(sizeof(*disp), GFP_KERNEL); disp 2328 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!disp) disp 2331 drivers/gpu/drm/nouveau/dispnv50/disp.c mutex_init(&disp->mutex); disp 2333 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_display(dev)->priv = disp; disp 2337 drivers/gpu/drm/nouveau/dispnv50/disp.c disp->disp = &nouveau_display(dev)->disp; disp 2344 drivers/gpu/drm/nouveau/dispnv50/disp.c 0, 0x0000, NULL, NULL, &disp->sync); disp 2346 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); disp 2348 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nouveau_bo_map(disp->sync); disp 2350 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_bo_unpin(disp->sync); disp 2353 drivers/gpu/drm/nouveau/dispnv50/disp.c nouveau_bo_ref(NULL, &disp->sync); disp 2360 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_core_new(drm, &disp->core); disp 2365 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass >= GV100_DISP) disp 2368 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass >= GF110_DISP) disp 8 drivers/gpu/drm/nouveau/dispnv50/disp.h struct nvif_disp *disp; disp 71 drivers/gpu/drm/nouveau/dispnv50/disp.h int nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, disp 214 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_disp *disp = nv50_disp(head->base.base.dev); disp 237 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.handle = disp->core->chan.vram.handle; disp 480 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_disp *disp = nv50_disp(dev); disp 490 drivers/gpu/drm/nouveau/dispnv50/head.c head->func = disp->core->func->head; disp 493 drivers/gpu/drm/nouveau/dispnv50/head.c if (disp->disp->object.oclass < GV100_DISP) { disp 514 drivers/gpu/drm/nouveau/dispnv50/head.c if (disp->disp->object.oclass >= GF110_DISP) disp 520 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); disp 203 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_disp *disp = nv50_disp(head->base.base.dev); disp 222 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.handle = disp->core->chan.vram.handle; disp 67 drivers/gpu/drm/nouveau/dispnv50/lut.c nv50_lut_init(struct nv50_disp *disp, struct nvif_mmu *mmu, disp 70 drivers/gpu/drm/nouveau/dispnv50/lut.c const u32 size = disp->disp->object.oclass < GF110_DISP ? 257 : 1025; disp 41 drivers/gpu/drm/nouveau/dispnv50/oimm.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 44 drivers/gpu/drm/nouveau/dispnv50/oimm.c cid = nvif_mclass(&disp->disp->object, oimms); disp 33 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 36 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, disp 43 drivers/gpu/drm/nouveau/dispnv50/ovly.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 46 drivers/gpu/drm/nouveau/dispnv50/ovly.c cid = nvif_mclass(&disp->disp->object, ovlys); disp 176 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 187 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, disp 189 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c disp->sync->bo.offset, &wndw->wndw); disp 38 drivers/gpu/drm/nouveau/dispnv50/wimm.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 41 drivers/gpu/drm/nouveau/dispnv50/wimm.c cid = nvif_mclass(&disp->disp->object, wimms); disp 67 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 70 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, disp 104 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_disp *disp = nv50_disp(wndw->plane.dev); disp 106 drivers/gpu/drm/nouveau/dispnv50/wndw.c return wndw->func->ntfy_wait_begun(disp->sync, disp 169 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_disp *disp = nv50_disp(wndw->plane.dev); disp 176 drivers/gpu/drm/nouveau/dispnv50/wndw.c wndw->func->ntfy_reset(disp->sync, wndw->ntfy); disp 636 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_disp *disp = nv50_disp(dev); disp 665 drivers/gpu/drm/nouveau/dispnv50/wndw.c ret = nv50_lut_init(disp, mmu, &wndw->ilut); disp 712 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 715 drivers/gpu/drm/nouveau/dispnv50/wndw.c cid = nvif_mclass(&disp->disp->object, wndws); disp 284 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c struct nv50_disp *disp = nv50_disp(drm->dev); disp 294 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, disp 296 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c disp->sync->bo.offset, &wndw->wndw); disp 29 drivers/gpu/drm/nouveau/include/nvif/if0008.h __u8 disp; disp 161 drivers/gpu/drm/nouveau/include/nvkm/core/device.h struct nvkm_disp *disp; disp 234 drivers/gpu/drm/nouveau/include/nvkm/core/device.h int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); disp 15 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h u32 disp; disp 103 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_display *disp = nouveau_display(connector->dev); disp 108 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->underscan_property) disp 110 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->underscan_hborder_property) disp 112 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->underscan_vborder_property) disp 114 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->dithering_mode) disp 116 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->dithering_depth) disp 118 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->vibrant_hue_property) disp 120 drivers/gpu/drm/nouveau/nouveau_connector.c else if (property == disp->color_vibrance_property) disp 135 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_display *disp = nouveau_display(dev); disp 154 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) disp 173 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->underscan_property) { disp 179 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->underscan_hborder_property) { disp 185 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->underscan_vborder_property) { disp 191 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->dithering_mode) { disp 197 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->dithering_depth) { disp 203 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->vibrant_hue_property) { disp 209 drivers/gpu/drm/nouveau/nouveau_connector.c if (property == disp->color_vibrance_property) { disp 271 drivers/gpu/drm/nouveau/nouveau_connector.c if (nouveau_display(connector->dev)->disp.object.oclass < NV50_DISP) { disp 287 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_display *disp = nouveau_display(dev); disp 302 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->underscan_property && disp 308 drivers/gpu/drm/nouveau/nouveau_connector.c disp->underscan_property, disp 311 drivers/gpu/drm/nouveau/nouveau_connector.c disp->underscan_hborder_property, 0); disp 313 drivers/gpu/drm/nouveau/nouveau_connector.c disp->underscan_vborder_property, 0); disp 317 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->vibrant_hue_property) disp 319 drivers/gpu/drm/nouveau/nouveau_connector.c disp->vibrant_hue_property, disp 321 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->color_vibrance_property) disp 323 drivers/gpu/drm/nouveau/nouveau_connector.c disp->color_vibrance_property, disp 331 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) disp 347 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->dithering_mode) { disp 349 drivers/gpu/drm/nouveau/nouveau_connector.c disp->dithering_mode, disp 352 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->dithering_depth) { disp 354 drivers/gpu/drm/nouveau/nouveau_connector.c disp->dithering_depth, disp 1260 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_display *disp = nouveau_display(dev); disp 1385 drivers/gpu/drm/nouveau/nouveau_connector.c if ((disp->disp.object.oclass >= G82_DISP) disp 1407 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) { disp 1438 drivers/gpu/drm/nouveau/nouveau_connector.c ret = nvif_notify_init(&disp->disp.object, nouveau_connector_hotplug, disp 111 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(crtc->dev); disp 117 drivers/gpu/drm/nouveau/nouveau_display.c ret = nvif_mthd(&disp->disp.object, 0, &args, sizeof(args)); disp 170 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 176 drivers/gpu/drm/nouveau/nouveau_display.c ret = nvif_notify_init(&disp->disp.object, disp 405 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 410 drivers/gpu/drm/nouveau/nouveau_display.c ret = disp->init(dev, resume, runtime); disp 433 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 457 drivers/gpu/drm/nouveau/nouveau_display.c disp->fini(dev, suspend); disp 463 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 466 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < NV50_DISP) disp 469 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < GF110_DISP) disp 474 drivers/gpu/drm/nouveau/nouveau_display.c PROP_ENUM(disp->dithering_mode, gen, "dithering mode", dither_mode); disp 475 drivers/gpu/drm/nouveau/nouveau_display.c PROP_ENUM(disp->dithering_depth, gen, "dithering depth", dither_depth); disp 476 drivers/gpu/drm/nouveau/nouveau_display.c PROP_ENUM(disp->underscan_property, gen, "underscan", underscan); disp 478 drivers/gpu/drm/nouveau/nouveau_display.c disp->underscan_hborder_property = disp 481 drivers/gpu/drm/nouveau/nouveau_display.c disp->underscan_vborder_property = disp 488 drivers/gpu/drm/nouveau/nouveau_display.c disp->vibrant_hue_property = disp 492 drivers/gpu/drm/nouveau/nouveau_display.c disp->color_vibrance_property = disp 501 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp; disp 504 drivers/gpu/drm/nouveau/nouveau_display.c disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL); disp 505 drivers/gpu/drm/nouveau/nouveau_display.c if (!disp) disp 545 drivers/gpu/drm/nouveau/nouveau_display.c ret = nvif_disp_ctor(&drm->client.device, 0, &disp->disp); disp 548 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < NV50_DISP) disp 577 drivers/gpu/drm/nouveau/nouveau_display.c disp->dtor(dev); disp 587 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 597 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->dtor) disp 598 drivers/gpu/drm/nouveau/nouveau_display.c disp->dtor(dev); disp 600 drivers/gpu/drm/nouveau/nouveau_display.c nvif_disp_dtor(&disp->disp); disp 603 drivers/gpu/drm/nouveau/nouveau_display.c kfree(disp); disp 609 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 613 drivers/gpu/drm/nouveau/nouveau_display.c disp->suspend = drm_atomic_helper_suspend(dev); disp 614 drivers/gpu/drm/nouveau/nouveau_display.c if (IS_ERR(disp->suspend)) { disp 615 drivers/gpu/drm/nouveau/nouveau_display.c int ret = PTR_ERR(disp->suspend); disp 616 drivers/gpu/drm/nouveau/nouveau_display.c disp->suspend = NULL; disp 629 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_display *disp = nouveau_display(dev); disp 634 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->suspend) { disp 635 drivers/gpu/drm/nouveau/nouveau_display.c drm_atomic_helper_resume(dev, disp->suspend); disp 636 drivers/gpu/drm/nouveau/nouveau_display.c disp->suspend = NULL; disp 38 drivers/gpu/drm/nouveau/nouveau_display.h struct nvif_disp disp; disp 28 drivers/gpu/drm/nouveau/nvif/disp.c nvif_disp_dtor(struct nvif_disp *disp) disp 30 drivers/gpu/drm/nouveau/nvif/disp.c nvif_object_fini(&disp->object); disp 34 drivers/gpu/drm/nouveau/nvif/disp.c nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) disp 55 drivers/gpu/drm/nouveau/nvif/disp.c disp->object.client = NULL; disp 60 drivers/gpu/drm/nouveau/nvif/disp.c NULL, 0, &disp->object); disp 103 drivers/gpu/drm/nouveau/nvif/mmu.c if (args.disp) mmu->type[i].type |= NVIF_MEM_DISP; disp 91 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 112 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 134 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 154 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 176 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 198 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 220 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 242 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 264 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 286 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 308 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 330 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 352 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 374 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 396 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 419 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 442 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 464 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 489 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 515 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 541 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 567 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 593 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 619 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 645 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 671 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 697 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 723 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 749 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 775 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 801 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 830 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv50_disp_new, disp 856 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 882 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 908 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = nv04_disp_new, disp 939 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g84_disp_new, disp 971 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g84_disp_new, disp 1003 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g84_disp_new, disp 1035 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g94_disp_new, disp 1067 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g94_disp_new, disp 1097 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = g94_disp_new, disp 1131 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt200_disp_new, disp 1163 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1197 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1230 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1261 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = mcp77_disp_new, disp 1293 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = mcp77_disp_new, disp 1327 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = mcp89_disp_new, disp 1364 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1400 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1436 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1473 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1510 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1547 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1583 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gt215_disp_new, disp 1618 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gf119_disp_new, disp 1654 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gf119_disp_new, disp 1693 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk104_disp_new, disp 1732 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk104_disp_new, disp 1771 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk104_disp_new, disp 1835 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk110_disp_new, disp 1873 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk110_disp_new, disp 1911 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk110_disp_new, disp 1949 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gk110_disp_new, disp 1986 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gm107_disp_new, disp 2020 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gm107_disp_new, disp 2055 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gm200_disp_new, disp 2090 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gm200_disp_new, disp 2125 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gm200_disp_new, disp 2187 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp100_disp_new, disp 2220 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp102_disp_new, disp 2256 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp102_disp_new, disp 2292 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp102_disp_new, disp 2328 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp102_disp_new, disp 2364 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gp102_disp_new, disp 2421 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = gv100_disp_new, disp 2466 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = tu102_disp_new, disp 2501 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = tu102_disp_new, disp 2536 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = tu102_disp_new, disp 2571 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = tu102_disp_new, disp 2606 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .disp = tu102_disp_new, disp 2695 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(DISP , device->disp , &device->disp->engine); disp 3183 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(NVKM_ENGINE_DISP , disp); disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); disp 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_head *head = nvkm_head_find(disp, id); disp 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); disp 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_head *head = nvkm_head_find(disp, id); disp 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = disp 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c container_of(notify->event, typeof(*disp), vblank); disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) { disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_vblank(struct nvkm_disp *disp, int head) disp 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep)); disp 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = disp 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c container_of(notify->event, typeof(*disp), hpd); disp 111 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(outp, &disp->outp, head) { disp 134 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(object->engine); disp 137 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c *event = &disp->vblank; disp 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c *event = &disp->hpd; disp 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine); disp 152 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c mutex_lock(&disp->engine.subdev.mutex); disp 153 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->client == oproxy) disp 154 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c disp->client = NULL; disp 155 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c mutex_unlock(&disp->engine.subdev.mutex); disp 169 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oclass->engine); disp 178 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c mutex_lock(&disp->engine.subdev.mutex); disp 179 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->client) { disp 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c mutex_unlock(&disp->engine.subdev.mutex); disp 183 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c disp->client = oproxy; disp 184 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c mutex_unlock(&disp->engine.subdev.mutex); disp 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c return sclass->ctor(disp, oclass, data, size, &oproxy->object); disp 198 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oclass->engine); disp 200 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c const struct nvkm_disp_oclass *root = disp->func->root(disp); disp 212 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(engine); disp 213 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c disp->func->intr(disp); disp 219 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(engine); disp 223 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->func->fini) disp 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c disp->func->fini(disp); disp 226 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(outp, &disp->outp, head) { disp 230 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(conn, &disp->conn, head) { disp 240 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(engine); disp 245 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(conn, &disp->conn, head) { disp 249 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(outp, &disp->outp, head) { disp 253 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->func->init) { disp 254 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c int ret = disp->func->init(disp); disp 262 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(ior, &disp->ior, head) { disp 272 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(engine); disp 273 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_subdev *subdev = &disp->engine.subdev; disp 301 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = nvkm_outp_new(disp, i, &dcbE, &outp); disp 304 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = nvkm_dp_new(disp, i, &dcbE, &outp); disp 329 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_add_tail(&outp->head, &disp->outp); disp 334 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry_safe(outp, outt, &disp->outp, head) { disp 348 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(pair, &disp->outp, head) { disp 368 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(conn, &disp->conn, head) { disp 379 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = nvkm_conn_new(disp, i, &connE, &outp->conn); disp 381 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_error(&disp->engine.subdev, disp 390 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_add_tail(&outp->conn->head, &disp->conn); disp 393 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = nvkm_event_init(&nvkm_disp_hpd_func, 3, hpd, &disp->hpd); disp 397 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->func->oneinit) { disp 398 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = disp->func->oneinit(disp); disp 406 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(outp, &disp->outp, head) { disp 409 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ior = nvkm_ior_find(disp, SOR, ffs(outp->info.or) - 1); disp 417 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_for_each_entry(head, &disp->head, head) disp 420 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c return nvkm_event_init(&nvkm_disp_vblank_func, 1, i, &disp->vblank); disp 426 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(engine); disp 429 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c void *data = disp; disp 431 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c if (disp->func->dtor) disp 432 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c data = disp->func->dtor(disp); disp 434 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_event_fini(&disp->vblank); disp 435 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_event_fini(&disp->hpd); disp 437 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c while (!list_empty(&disp->conn)) { disp 438 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c conn = list_first_entry(&disp->conn, typeof(*conn), head); disp 443 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c while (!list_empty(&disp->outp)) { disp 444 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c outp = list_first_entry(&disp->outp, typeof(*outp), head); disp 449 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c while (!list_empty(&disp->ior)) { disp 451 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_first_entry(&disp->ior, typeof(*ior), head); disp 455 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c while (!list_empty(&disp->head)) { disp 457 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c list_first_entry(&disp->head, typeof(*head), head); disp 476 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c int index, struct nvkm_disp *disp) disp 478 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c disp->func = func; disp 479 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c INIT_LIST_HEAD(&disp->head); disp 480 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c INIT_LIST_HEAD(&disp->ior); disp 481 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c INIT_LIST_HEAD(&disp->outp); disp 482 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c INIT_LIST_HEAD(&disp->conn); disp 483 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c return nvkm_engine_ctor(&nvkm_disp, device, index, true, &disp->engine); disp 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c disp, 1, oclass, argv, argc, pobject); disp 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c disp, 1, oclass, argv, argc, pobject); disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c disp, 1, oclass, argv, argc, pobject); disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c struct nv50_disp *disp, int chid, disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) disp 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid + head, disp 115 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c disp, 1, oclass, argv, argc, pobject); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); disp 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c, disp 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = chan->disp; disp 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_mthd_list(disp, debug, base, mthd->prev, disp 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); disp 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_chan_uevent_send(struct nv50_disp *disp, int chid) disp 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_event_send(&disp->uevent, 1, chid, &rep, sizeof(rep)); disp 170 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 190 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = chan->disp; disp 204 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c *pevent = &disp->uevent; disp 217 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 226 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp; disp 235 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_ramht_remove(object->disp->ramht, object->hash); disp 248 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = chan->disp; disp 249 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 257 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c object->disp = disp; disp 277 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 318 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp = chan->disp; disp 320 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c disp->chan[chan->chid.user] = NULL; disp 340 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp *disp, int ctrl, int user, int head, disp 353 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c chan->disp = disp; disp 358 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (disp->chan[chan->chid.user]) { disp 362 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c disp->chan[chan->chid.user] = chan; disp 12 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h struct nv50_disp *disp; disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c struct nvkm_disp *disp = conn->disp; disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c struct nvkm_gpio *gpio = disp->engine.subdev.device->gpio; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep)); disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c nvkm_conn_ctor(struct nvkm_disp *disp, int index, struct nvbios_connE *info, disp 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c struct nvkm_gpio *gpio = disp->engine.subdev.device->gpio; disp 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c conn->disp = disp; disp 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c nvkm_conn_new(struct nvkm_disp *disp, int index, struct nvbios_connE *info, disp 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c nvkm_conn_ctor(disp, index, info, *pconn); disp 11 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h struct nvkm_disp *disp; disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h nvkm_##l(&_conn->disp->engine.subdev, "conn %02x:%02x%02x: "f"\n", \ disp 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c disp, 0, oclass, argv, argc, pobject); disp 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c disp, 0, oclass, argv, argc, pobject); disp 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 190 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 225 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 228 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c disp, 0, oclass, argv, argc, pobject); disp 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c disp, 0, oclass, argv, argc, pobject); disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c disp, 0, oclass, argv, argc, pobject); disp 138 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 157 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 166 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 200 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 203 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c disp, 0, oclass, argv, argc, pobject); disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nv50_disp *disp, int chid, disp 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid, 0, disp 169 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 187 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 228 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 231 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c disp, 0, oclass, argv, argc, pobject); disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 13, disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 17, disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 79 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c return nv50_disp_curs_new_(&gv100_disp_curs, disp, 73, 73, disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c struct nv50_disp *disp, int ctrl, int user, disp 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) disp 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c return nv50_disp_chan_new_(func, NULL, disp, ctrl + head, user + head, disp 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c return nv50_disp_curs_new_(&nv50_disp_pioc_func, disp, 7, 7, disp 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c gf119_dac_new(struct nvkm_disp *disp, int id) disp 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c return nvkm_ior_new_(&gf119_dac, disp, DAC, id); disp 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c gf119_dac_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c struct nvkm_device *device = disp->engine.subdev.device; disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c struct nvkm_device *device = dac->disp->engine.subdev.device; disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c nv50_dac_new(struct nvkm_disp *disp, int id) disp 112 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c return nvkm_ior_new_(&nv50_dac, disp, DAC, id); disp 116 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c nv50_dac_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c struct nvkm_device *device = disp->engine.subdev.device; disp 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c return nvkm_ramht_insert(chan->disp->ramht, object, disp 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c return nvkm_ramht_insert(chan->disp->ramht, object, disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nv50_disp *disp, int chid, int head, u64 push, disp 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c ret = nv50_disp_chan_new_(func, mthd, disp, chid, chid, head, oclass, disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c return nvkm_ramht_insert(chan->disp->ramht, object, disp 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios; disp 223 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_disp *disp = dp->outp.disp; disp 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_subdev *subdev = &disp->engine.subdev; disp 237 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (disp->engine.subdev.device->chipset < 0xd0) disp 294 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[1], disp 306 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[2], disp 312 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[3], disp 320 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0], disp 428 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvbios_init(&ior->disp->engine.subdev, dp->info.script[4], disp 461 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c list_for_each_entry(head, &outp->disp->head, head) { disp 541 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_disp *disp = dp->outp.disp; disp 558 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep)); disp 573 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio; disp 627 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_ctor(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, disp 630 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_device *device = disp->engine.subdev.device; disp 637 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_outp_ctor(&nvkm_dp_func, disp, index, dcbE, &dp->outp); disp 680 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, disp 683 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c; disp 696 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c return nvkm_dp_ctor(disp, index, dcbE, aux, dp); disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nv50_disp *disp = disp 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super)); disp 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (disp->super & 0x00000001) { disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_1(disp); disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_1_0(disp, head); disp 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (disp->super & 0x00000002) { disp 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_2_0(disp, head); disp 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_outp_route(&disp->base); disp 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_2_1(disp, head); disp 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_2_2(disp, head); disp 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (disp->super & 0x00000004) { disp 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_super_3_0(disp, head); disp 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) disp 90 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c gf119_disp_intr_error(struct nv50_disp *disp, int chid) disp 92 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (chid < ARRAY_SIZE(disp->chan)) { disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); disp 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c gf119_disp_intr(struct nv50_disp *disp) disp 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 133 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nv50_disp_chan_uevent_send(disp, chid); disp 143 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c disp->func->intr_error(disp, chid); disp 150 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c disp->super = (stat & 0x00000007); disp 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c queue_work(disp->wq, &disp->supervisor); disp 152 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_wr32(device, 0x6100ac, disp->super); disp 164 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 170 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_disp_vblank(&disp->base, head->id); disp 178 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c gf119_disp_fini(struct nv50_disp *disp) disp 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c gf119_disp_init(struct nv50_disp *disp) disp 188 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 199 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 210 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c for (i = 0; i < disp->dac.nr; i++) { disp 216 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c for (i = 0; i < disp->sor.nr; i++) { disp 233 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9); disp 246 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c gp102_disp_intr_error(struct nv50_disp *disp, int chid) disp 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c if (chid < ARRAY_SIZE(disp->chan)) { disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_device *device = disp->engine.subdev.device; disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nv50_disp *disp = disp 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super), stat); disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (disp->super & 0x00000001) { disp 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); disp 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_1(disp); disp 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_1_0(disp, head); disp 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (disp->super & 0x00000002) { disp 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_2_0(disp, head); disp 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_outp_route(&disp->base); disp 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_2_1(disp, head); disp 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_2_2(disp, head); disp 83 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (disp->super & 0x00000004) { disp 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_super_3_0(disp, head); disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) disp 97 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_exception(struct nv50_disp *disp, int chid) disp 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { disp 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); disp 128 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_ctrl_disp(struct nv50_disp *disp) disp 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 135 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c disp->super = (stat & 0x00000007); disp 136 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c queue_work(disp->wq, &disp->supervisor); disp 137 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611860, disp->super); disp 157 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_chan_uevent_send(disp, 0); disp 160 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(wndw, &wndws, disp->wndw.nr) { disp 161 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nv50_disp_chan_uevent_send(disp, 1 + wndw); disp 170 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_other(struct nv50_disp *disp) disp 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_exception(disp, 0); disp 185 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(head, &mask, disp->wndw.nr) { disp 187 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_exception(disp, 73 + head); disp 199 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_winim(struct nv50_disp *disp) disp 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 206 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(wndw, &stat, disp->wndw.nr) { disp 208 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_exception(disp, 33 + wndw); disp 219 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_win(struct nv50_disp *disp) disp 221 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 226 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(wndw, &stat, disp->wndw.nr) { disp 228 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_exception(disp, 1 + wndw); disp 239 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_head_timing(struct nv50_disp *disp, int head) disp 241 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 252 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_disp_vblank(&disp->base, head); disp 264 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr(struct nv50_disp *disp) disp 266 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 274 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_head_timing(disp, head); disp 280 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_win(disp); disp 285 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_winim(disp); disp 290 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_exc_other(disp); disp 295 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_intr_ctrl_disp(disp); disp 304 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_fini(struct nv50_disp *disp) disp 306 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 311 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c gv100_disp_init(struct nv50_disp *disp) disp 313 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 333 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for (i = 0; i < disp->sor.nr; i++) { disp 340 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 355 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for (i = 0; i < disp->wndw.nr; i++) { disp 372 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c switch (nvkm_memory_target(disp->inst->memory)) { disp 380 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); disp 387 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | disp 392 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ disp 396 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ disp 400 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c struct nvkm_device *device = ior->disp->engine.subdev.device; disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c nvkm_head_find(struct nvkm_disp *disp, int id) disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c list_for_each_entry(head, &disp->head, head) { disp 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c struct nvkm_disp *disp, int id) disp 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c head->disp = disp; disp 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c list_add_tail(&head->head, &disp->head); disp 8 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h struct nvkm_disp *disp; disp 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h nvkm_##l(&_h->disp->engine.subdev, "head-%d: "f"\n", _h->id, ##a); \ disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c gf119_head_new(struct nvkm_disp *disp, int id) disp 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c return nvkm_head_new_(&gf119_head, disp, id); disp 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c gf119_head_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c struct nvkm_device *device = disp->engine.subdev.device; disp 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c gv100_head_new(struct nvkm_disp *disp, int id) disp 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = disp->engine.subdev.device; disp 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c return nvkm_head_new_(&gv100_head, disp, id); disp 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c gv100_head_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c struct nvkm_device *device = disp->engine.subdev.device; disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c nv04_head_new(struct nvkm_disp *disp, int id) disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c return nvkm_head_new_(&nv04_head, disp, id); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c struct nvkm_device *device = head->disp->engine.subdev.device; disp 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c nv50_head_new(struct nvkm_disp *disp, int id) disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c return nvkm_head_new_(&nv50_head, disp, id); disp 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c nv50_head_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c nvkm_ior_find(struct nvkm_disp *disp, enum nvkm_ior_type type, int id) disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c list_for_each_entry(ior, &disp->ior, head) { disp 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c nvkm_ior_new_(const struct nvkm_ior_func *func, struct nvkm_disp *disp, disp 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c ior->disp = disp; disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c list_add_tail(&ior->head, &disp->ior); disp 9 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h struct nvkm_disp *disp; disp 168 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h nvkm_##l(&_ior->disp->engine.subdev, "%s: "f"\n", _ior->name, ##a); \ disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c nv04_disp_root(struct nvkm_disp *disp) disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c nv04_disp_intr(struct nvkm_disp *disp) disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c struct nvkm_subdev *subdev = &disp->engine.subdev; disp 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c nvkm_disp_vblank(disp, 0); disp 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c nvkm_disp_vblank(disp, 1); disp 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); disp 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->func->intr(disp); disp 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); disp 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->func->fini(disp); disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); disp 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c return disp->func->init(disp); disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); disp 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_ramht_del(&disp->ramht); disp 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_gpuobj_del(&disp->inst); disp 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_event_fini(&disp->uevent); disp 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (disp->wq) disp 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c destroy_workqueue(disp->wq); disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c return disp; disp 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); disp 85 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c const struct nv50_disp_func *func = disp->func; disp 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wndw.nr = func->wndw.cnt(&disp->base, &disp->wndw.mask); disp 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wndw.nr, disp->wndw.mask); disp 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->head.nr = func->head.cnt(&disp->base, &disp->head.mask); disp 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->head.nr, disp->head.mask); disp 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->head.mask, disp->head.nr) { disp 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->head.new(&disp->base, i); disp 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->dac.nr = func->dac.cnt(&disp->base, &disp->dac.mask); disp 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->dac.nr, disp->dac.mask); disp 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->dac.mask, disp->dac.nr) { disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->dac.new(&disp->base, i); disp 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr = func->pior.cnt(&disp->base, &disp->pior.mask); disp 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr, disp->pior.mask); disp 120 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->pior.mask, disp->pior.nr) { disp 121 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->pior.new(&disp->base, i); disp 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr = func->sor.cnt(&disp->base, &disp->sor.mask); disp 129 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr, disp->sor.mask); disp 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->sor.mask, disp->sor.nr) { disp 131 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->sor.new(&disp->base, i); disp 137 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c &disp->inst); disp 142 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 0x1000, 0, disp->inst, &disp->ramht); disp 159 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp; disp 162 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL))) disp 164 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->func = func; disp 165 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c *pdisp = &disp->base; disp 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base); disp 171 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wq = create_singlethread_workqueue("nvkm-disp"); disp 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (!disp->wq) disp 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c INIT_WORK(&disp->supervisor, func->super); disp 177 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c return nvkm_event_init(func->uevent, 1, ARRAY_SIZE(disp->chan), disp 178 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c &disp->uevent); disp 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_bios *bios = head->disp->engine.subdev.device->bios; disp 200 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &head->disp->engine.subdev; disp 269 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvbios_init(&head->disp->engine.subdev, iedt.script[id], disp 281 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(ior, &head->disp->ior, head) { disp 295 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(ior, &head->disp->ior, head) { disp 306 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_3_0(struct nv50_disp *disp, struct nvkm_head *head) disp 327 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &head->disp->engine.subdev; disp 431 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_2(struct nv50_disp *disp, struct nvkm_head *head) disp 453 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18; disp 454 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ior->asy.link = (disp->sor.lvdsconf & 0x0100) ? 3 : 1; disp 478 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_1(struct nv50_disp *disp, struct nvkm_head *head) disp 480 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_devinit *devinit = disp->base.engine.subdev.device->devinit; disp 488 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_0(struct nv50_disp *disp, struct nvkm_head *head) disp 512 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_1_0(struct nv50_disp *disp, struct nvkm_head *head) disp 527 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_1(struct nv50_disp *disp) disp 532 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 537 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(ior, &disp->base.ior, head) { disp 546 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = disp 548 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 553 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super); disp 555 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (disp->super & 0x00000010) { disp 556 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); disp 557 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_1(disp); disp 558 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 563 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_1_0(disp, head); disp 566 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (disp->super & 0x00000020) { disp 567 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 570 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_0(disp, head); disp 572 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_outp_route(&disp->base); disp 573 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 576 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_1(disp, head); disp 578 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 581 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_2_2(disp, head); disp 584 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (disp->super & 0x00000040) { disp 585 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 588 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_3_0(disp, head); disp 614 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_intr_error(struct nv50_disp *disp, int chid) disp 616 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 633 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (chid < ARRAY_SIZE(disp->chan)) { disp 636 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); disp 648 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_intr(struct nv50_disp *disp) disp 650 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 656 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_intr_error(disp, chid); disp 662 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_chan_uevent_send(disp, chid); disp 667 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_disp_vblank(&disp->base, 0); disp 672 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_disp_vblank(&disp->base, 1); disp 677 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->super = (intr1 & 0x00000070); disp 678 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c queue_work(disp->wq, &disp->supervisor); disp 679 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_wr32(device, 0x610024, disp->super); disp 684 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_fini(struct nv50_disp *disp) disp 686 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 693 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_init(struct nv50_disp *disp) disp 695 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 708 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { disp 720 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for (i = 0; i < disp->dac.nr; i++) { disp 726 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for (i = 0; i < disp->sor.nr; i++) { disp 732 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for (i = 0; i < disp->pior.nr; i++) { disp 749 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9); disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 9, disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 13, disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c struct nv50_disp *disp, int ctrl, int user, disp 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) disp 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c return nv50_disp_chan_new_(func, NULL, disp, ctrl + head, user + head, disp 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c return nv50_disp_oimm_new_(&nv50_disp_pioc_func, disp, 5, 5, disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c nvkm_outp_route(struct nvkm_disp *disp) disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c list_for_each_entry(ior, &disp->ior, head) { disp 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c list_for_each_entry(ior, &disp->ior, head) { disp 134 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c ior = nvkm_ior_find(outp->disp, SOR, ffs(outp->info.or) - 1); disp 143 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c list_for_each_entry(ior, &outp->disp->ior, head) { disp 149 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c list_for_each_entry(ior, &outp->disp->ior, head) { disp 159 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c list_for_each_entry(ior, &outp->disp->ior, head) { disp 178 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c struct nvkm_disp *disp = outp->disp; disp 189 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c ior = nvkm_ior_find(disp, type, -1); disp 208 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c ior = nvkm_ior_find(disp, type, id); disp 247 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c nvkm_outp_ctor(const struct nvkm_outp_func *func, struct nvkm_disp *disp, disp 250 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c; disp 255 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c outp->disp = disp; disp 280 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c nvkm_outp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, disp 285 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c return nvkm_outp_ctor(&nvkm_outp, disp, index, dcbE, *poutp); disp 11 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h struct nvkm_disp *disp; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h nvkm_##l(&_outp->disp->engine.subdev, "outp %02x:%04x:%04x: "f"\n", \ disp 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c disp, 3, oclass, argv, argc, pobject); disp 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c disp, 5, oclass, argv, argc, pobject); disp 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c disp, 5, oclass, argv, argc, pobject); disp 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c disp, 5, oclass, argv, argc, pobject); disp 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c disp, 3, oclass, argv, argc, pobject); disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c struct nv50_disp *disp, int chid, disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) disp 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c return nv50_disp_dmac_new_(func, mthd, disp, chid + head, disp 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c disp, 3, oclass, argv, argc, pobject); disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nv50_disp *disp = chan->disp; disp 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nv50_disp *disp = chan->disp; disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nv50_disp *disp = chan->disp; disp 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nv50_disp *disp = chan->disp; disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; disp 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; disp 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; disp 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nvkm_head_find(ior->disp, __ffs(state->head)); disp 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; disp 128 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_new(struct nvkm_disp *disp, int id) disp 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c return nvkm_ior_new_(&nv50_pior, disp, PIOR, id); disp 134 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 136 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = disp->engine.subdev.device; disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c g84_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c return nv50_disp_root_new_(&g84_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c g94_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c return nv50_disp_root_new_(&g94_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c return nv50_disp_root_new_(&gf119_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c gk104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c return nv50_disp_root_new_(&gk104_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c gk110_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c return nv50_disp_root_new_(&gk110_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c gm107_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c return nv50_disp_root_new_(&gm107_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c gm200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c return nv50_disp_root_new_(&gm200_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c gp100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c return nv50_disp_root_new_(&gp100_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c gp102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c return nv50_disp_root_new_(&gp102_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c gt200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c return nv50_disp_root_new_(>200_disp_root, disp, oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c gt215_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c return nv50_disp_root_new_(>215_disp_root, disp, oclass, disp 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c gv100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c return nv50_disp_root_new_(&gv100_disp_root, disp, oclass, disp 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c struct nvkm_disp *disp; disp 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c if (!(head = nvkm_head_find(root->disp, id))) disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c nv04_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 85 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c root->disp = disp; disp 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nv50_disp *disp = root->disp; disp 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c if (!(head = nvkm_head_find(&disp->base, hidx))) disp 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c list_for_each_entry(temp, &disp->base.outp, head) { disp 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c disp->sor.lvdsconf = args->v0.script; disp 281 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nv50_disp *disp = nv50_disp_root(oclass->parent)->disp; disp 283 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c return user->ctor(oclass, argv, argc, disp, pobject); disp 322 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nv50_disp *disp = nv50_disp(base); disp 331 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c root->disp = disp; disp 348 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c nv50_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 351 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c return nv50_disp_root_new_(&nv50_disp_root, disp, oclass, disp 10 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h struct nv50_disp *disp; disp 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c tu102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, disp 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c return nv50_disp_root_new_(&tu102_disp_root, disp, oclass, disp 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c g84_sor_new(struct nvkm_disp *disp, int id) disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c return nvkm_ior_new_(&g84_sor, disp, SOR, id); disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_update_sppll1(struct nvkm_disp *disp) disp 142 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = disp->engine.subdev.device; disp 147 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c list_for_each_entry(ior, &disp->ior, head) { disp 171 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 207 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_update_sppll1(sor->disp); disp 213 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 239 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 280 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_new(struct nvkm_disp *disp, int id) disp 282 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c return nvkm_ior_new_(&g94_sor, disp, SOR, id); disp 286 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 288 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = disp->engine.subdev.device; disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 138 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 184 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_new(struct nvkm_disp *disp, int id) disp 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c return nvkm_ior_new_(&gf119_sor, disp, SOR, id); disp 190 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 192 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = disp->engine.subdev.device; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c gk104_sor_new(struct nvkm_disp *disp, int id) disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c return nvkm_ior_new_(&gk104_sor, disp, SOR, id); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c gm107_sor_new(struct nvkm_disp *disp, int id) disp 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c return nvkm_ior_new_(&gm107_sor, disp, SOR, id); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c struct nvkm_device *device = outp->disp->engine.subdev.device; disp 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c struct nvkm_device *device = outp->disp->engine.subdev.device; disp 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c gm200_sor_new(struct nvkm_disp *disp, int id) disp 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c return nvkm_ior_new_(&gm200_sor, disp, SOR, id); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c gt215_sor_new(struct nvkm_disp *disp, int id) disp 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c return nvkm_ior_new_(>215_sor, disp, SOR, id); disp 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_new(struct nvkm_disp *disp, int id) disp 112 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c return nvkm_ior_new_(&gv100_sor, disp, SOR, id); disp 116 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = disp->engine.subdev.device; disp 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c mcp77_sor_new(struct nvkm_disp *disp, int id) disp 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c return nvkm_ior_new_(&mcp77_sor, disp, SOR, id); disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c mcp89_sor_new(struct nvkm_disp *disp, int id) disp 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c return nvkm_ior_new_(&mcp89_sor, disp, SOR, id); disp 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c nv50_sor_new(struct nvkm_disp *disp, int id) disp 97 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c return nvkm_ior_new_(&nv50_sor, disp, SOR, id); disp 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c nv50_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) disp 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = disp->engine.subdev.device; disp 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c struct nvkm_device *device = sor->disp->engine.subdev.device; disp 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c tu102_sor_new(struct nvkm_disp *disp, int id) disp 97 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c return nvkm_ior_new_(&tu102_sor, disp, SOR, id); disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c tu102_disp_init(struct nv50_disp *disp) disp 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c struct nvkm_device *device = disp->base.engine.subdev.device; disp 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c for (i = 0; i < disp->sor.nr; i++) { disp 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c list_for_each_entry(head, &disp->base.head, head) { disp 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c for (i = 0; i < disp->wndw.nr; i++) { disp 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c switch (nvkm_memory_target(disp->inst->memory)) { disp 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); disp 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | disp 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ disp 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ disp 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c list_for_each_entry(head, &disp->base.head, head) { disp 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c struct nv50_disp *disp, int chid, disp 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) disp 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c return nv50_disp_dmac_new_(func, mthd, disp, chid + wndw, disp 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c return gv100_disp_wimm_new_(&gv100_disp_wimm, NULL, disp, 33, disp 133 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; disp 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c struct nv50_disp *disp, int chid, disp 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) disp 174 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c return nv50_disp_dmac_new_(func, mthd, disp, chid + wndw, disp 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c struct nv50_disp *disp, struct nvkm_object **pobject) disp 183 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c disp, 1, oclass, argv, argc, pobject); disp 43 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c u32 disp = nvkm_rd32(device, sec2->addr + 0x01c); disp 44 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c u32 intr = nvkm_rd32(device, sec2->addr + 0x008) & disp & ~(disp >> 16); disp 75 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c if (data < device->disp->vblank.index_nr) { disp 109 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c struct nvkm_disp *disp = sw->engine.subdev.device->disp; disp 122 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c for (i = 0; disp && i < disp->vblank.index_nr; i++) { disp 123 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c ret = nvkm_notify_init(NULL, &disp->vblank, disp 72 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c if (data < device->disp->vblank.index_nr) { disp 103 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c struct nvkm_disp *disp = sw->engine.subdev.device->disp; disp 115 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c for (i = 0; disp && i < disp->vblank.index_nr; i++) { disp 116 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c ret = nvkm_notify_init(NULL, &disp->vblank, disp 146 drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c info->disp = nvbios_rd16(bios, perf + 0x14) * 1000; disp 434 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c cstate->domain[nv_clk_src_dom6] = perfE.disp; disp 94 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c args->v0.disp = !!(type & NVKM_MEM_DISP); disp 143 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 disp = nvkm_rd32(device, 0x10a01c); disp 144 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); disp 49 drivers/gpu/ipu-v3/ipu-dc.c #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4) disp 50 drivers/gpu/ipu-v3/ipu-dc.c #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4) disp 673 drivers/gpu/ipu-v3/ipu-di.c struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) disp 677 drivers/gpu/ipu-v3/ipu-di.c if (disp > 1) disp 680 drivers/gpu/ipu-v3/ipu-di.c di = ipu->di_priv[disp]; disp 257 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp = layer->disp_dev; disp 265 drivers/media/platform/davinci/vpbe_display.c spin_lock_irqsave(&disp->dma_queue_lock, flags); disp 267 drivers/media/platform/davinci/vpbe_display.c spin_unlock_irqrestore(&disp->dma_queue_lock, flags); disp 317 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp = layer->disp_dev; disp 326 drivers/media/platform/davinci/vpbe_display.c spin_lock_irqsave(&disp->dma_queue_lock, flags); disp 346 drivers/media/platform/davinci/vpbe_display.c spin_unlock_irqrestore(&disp->dma_queue_lock, flags); disp 577 drivers/net/ppp/bsd_comp.c int disp; disp 674 drivers/net/ppp/bsd_comp.c disp = (hval == 0) ? 1 : hval; disp 678 drivers/net/ppp/bsd_comp.c hval += disp; disp 1056 drivers/net/ppp/bsd_comp.c int hval, disp, indx; disp 1065 drivers/net/ppp/bsd_comp.c disp = (hval == 0) ? 1 : hval; disp 1068 drivers/net/ppp/bsd_comp.c hval += disp; disp 319 drivers/platform/x86/eeepc-laptop.c EEEPC_CREATE_DEVICE_ATTR_WO(disp, CM_ASL_DISPLAYSWITCH); disp 873 drivers/s390/char/tape_34xx.c struct display_struct disp; disp 875 drivers/s390/char/tape_34xx.c if (copy_from_user(&disp, (char __user *) arg, sizeof(disp)) != 0) disp 878 drivers/s390/char/tape_34xx.c return tape_std_display(device, &disp); disp 470 drivers/s390/char/tape_3590.c struct display_struct disp; disp 472 drivers/s390/char/tape_3590.c if (copy_from_user(&disp, (char __user *) arg, sizeof(disp))) disp 475 drivers/s390/char/tape_3590.c return tape_std_display(device, &disp); disp 125 drivers/s390/char/tape_std.c tape_std_display(struct tape_device *device, struct display_struct *disp) disp 137 drivers/s390/char/tape_std.c *(unsigned char *) request->cpdata = disp->cntrl; disp 138 drivers/s390/char/tape_std.c DBF_EVENT(5, "TAPE: display cntrl=%04x\n", disp->cntrl); disp 139 drivers/s390/char/tape_std.c memcpy(((unsigned char *) request->cpdata) + 1, disp->message1, 8); disp 140 drivers/s390/char/tape_std.c memcpy(((unsigned char *) request->cpdata) + 9, disp->message2, 8); disp 110 drivers/s390/char/tape_std.h int tape_std_display(struct tape_device *, struct display_struct *disp); disp 88 drivers/staging/sm750fb/ddk750_display.c static void sw_panel_power_sequence(int disp, int delay) disp 94 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); disp 99 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0); disp 104 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0); disp 109 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); disp 12 drivers/video/display_timing.c void display_timings_release(struct display_timings *disp) disp 14 drivers/video/display_timing.c if (disp->timings) { disp 17 drivers/video/display_timing.c for (i = 0; i < disp->num_timings; i++) disp 18 drivers/video/display_timing.c kfree(disp->timings[i]); disp 19 drivers/video/display_timing.c kfree(disp->timings); disp 21 drivers/video/display_timing.c kfree(disp); disp 211 drivers/video/fbdev/clps711x-fb.c struct device_node *disp, *np = dev->of_node; disp 278 drivers/video/fbdev/clps711x-fb.c disp = of_parse_phandle(np, "display", 0); disp 279 drivers/video/fbdev/clps711x-fb.c if (!disp) { disp 285 drivers/video/fbdev/clps711x-fb.c ret = of_get_fb_videomode(disp, &cfb->mode, OF_USE_NATIVE_MODE); disp 287 drivers/video/fbdev/clps711x-fb.c of_node_put(disp); disp 291 drivers/video/fbdev/clps711x-fb.c of_property_read_u32(disp, "ac-prescale", &cfb->ac_prescale); disp 292 drivers/video/fbdev/clps711x-fb.c cfb->cmap_invert = of_property_read_bool(disp, "cmap-invert"); disp 294 drivers/video/fbdev/clps711x-fb.c ret = of_property_read_u32(disp, "bits-per-pixel", disp 296 drivers/video/fbdev/clps711x-fb.c of_node_put(disp); disp 922 drivers/video/fbdev/core/fbcon.c static int var_to_display(struct fbcon_display *disp, disp 926 drivers/video/fbdev/core/fbcon.c disp->xres_virtual = var->xres_virtual; disp 927 drivers/video/fbdev/core/fbcon.c disp->yres_virtual = var->yres_virtual; disp 928 drivers/video/fbdev/core/fbcon.c disp->bits_per_pixel = var->bits_per_pixel; disp 929 drivers/video/fbdev/core/fbcon.c disp->grayscale = var->grayscale; disp 930 drivers/video/fbdev/core/fbcon.c disp->nonstd = var->nonstd; disp 931 drivers/video/fbdev/core/fbcon.c disp->accel_flags = var->accel_flags; disp 932 drivers/video/fbdev/core/fbcon.c disp->height = var->height; disp 933 drivers/video/fbdev/core/fbcon.c disp->width = var->width; disp 934 drivers/video/fbdev/core/fbcon.c disp->red = var->red; disp 935 drivers/video/fbdev/core/fbcon.c disp->green = var->green; disp 936 drivers/video/fbdev/core/fbcon.c disp->blue = var->blue; disp 937 drivers/video/fbdev/core/fbcon.c disp->transp = var->transp; disp 938 drivers/video/fbdev/core/fbcon.c disp->rotate = var->rotate; disp 939 drivers/video/fbdev/core/fbcon.c disp->mode = fb_match_mode(var, &info->modelist); disp 940 drivers/video/fbdev/core/fbcon.c if (disp->mode == NULL) disp 947 drivers/video/fbdev/core/fbcon.c struct fbcon_display *disp) disp 949 drivers/video/fbdev/core/fbcon.c fb_videomode_to_var(var, disp->mode); disp 950 drivers/video/fbdev/core/fbcon.c var->xres_virtual = disp->xres_virtual; disp 951 drivers/video/fbdev/core/fbcon.c var->yres_virtual = disp->yres_virtual; disp 952 drivers/video/fbdev/core/fbcon.c var->bits_per_pixel = disp->bits_per_pixel; disp 953 drivers/video/fbdev/core/fbcon.c var->grayscale = disp->grayscale; disp 954 drivers/video/fbdev/core/fbcon.c var->nonstd = disp->nonstd; disp 955 drivers/video/fbdev/core/fbcon.c var->accel_flags = disp->accel_flags; disp 956 drivers/video/fbdev/core/fbcon.c var->height = disp->height; disp 957 drivers/video/fbdev/core/fbcon.c var->width = disp->width; disp 958 drivers/video/fbdev/core/fbcon.c var->red = disp->red; disp 959 drivers/video/fbdev/core/fbcon.c var->green = disp->green; disp 960 drivers/video/fbdev/core/fbcon.c var->blue = disp->blue; disp 961 drivers/video/fbdev/core/fbcon.c var->transp = disp->transp; disp 962 drivers/video/fbdev/core/fbcon.c var->rotate = disp->rotate; disp 2843 drivers/video/fbdev/core/fbcon.c struct fbcon_display *disp = &fb_display[fg_console]; disp 2881 drivers/video/fbdev/core/fbcon.c fbcon_redraw_softback(vc, disp, lines); disp 2903 drivers/video/fbdev/core/fbcon.c offset = disp->yscroll - scrollback_current; disp 2904 drivers/video/fbdev/core/fbcon.c limit = disp->vrows; disp 2905 drivers/video/fbdev/core/fbcon.c switch (disp->scrollmode) { disp 67 drivers/video/fbdev/mb862xx/mb862xxfb.h void __iomem *disp; disp 315 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c outreg(disp, GC_L0EM, 3); disp 98 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0PAL0 + (regno * 4), val); disp 213 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 215 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 219 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 222 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 230 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0M, reg); disp 233 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0EM); disp 234 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); disp 236 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_WY_WX, 0); disp 238 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_WH_WW, reg); disp 239 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0OA0, 0); disp 240 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0DA0, 0); disp 241 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0DY_L0DX, 0); disp 242 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WY_L0WX, 0); disp 243 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WH_L0WW, reg); disp 246 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_CPM_CUTC); disp 248 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_CPM_CUTC, reg); disp 252 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_HDB_HDP, reg); disp 254 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_VDP_VSP, reg); disp 257 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_VSW_HSW_HSP, reg); disp 258 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0)); disp 259 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0)); disp 262 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 265 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 276 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WY_L0WX, reg); disp 279 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WH_L0WW, reg); disp 292 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 294 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 297 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 299 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 334 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c l1em = inreg(disp, GC_L1EM); disp 346 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c l1em = inreg(disp, GC_L1EM); disp 359 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L1EM, l1em); disp 364 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L1DA, par->cap_buf); disp 369 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS | disp 371 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L1WY_L1WX, disp 373 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L1WH_L1WW, disp 375 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DLS, 1); disp 378 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) | disp 383 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, disp 384 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c inreg(disp, GC_DCM1) & ~GC_DCM1_L1E); disp 441 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 449 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1; disp 450 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_VDP_VSP); disp 455 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0EM); disp 459 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0M); disp 465 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_VSW_HSW_HSP); disp 469 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1; disp 472 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1; disp 553 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); disp 557 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); disp 561 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); disp 633 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c par->disp = par->mmio_base + MB862XX_DISP_BASE; disp 792 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 794 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 847 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c par->disp = par->mmio_base + MB862XX_DISP_BASE; disp 870 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 928 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c par->disp = par->mmio_base + MB86297_DISP0_BASE; disp 1136 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); disp 1138 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); disp 2102 drivers/video/fbdev/pxafb.c static int of_get_pxafb_display(struct device *dev, struct device_node *disp, disp 2110 drivers/video/fbdev/pxafb.c ret = of_property_read_string(disp, "lcd-type", &s); disp 2122 drivers/video/fbdev/pxafb.c timings = of_get_display_timings(disp); disp 148 drivers/video/of_display_timing.c struct display_timings *disp; disp 159 drivers/video/of_display_timing.c disp = kzalloc(sizeof(*disp), GFP_KERNEL); disp 160 drivers/video/of_display_timing.c if (!disp) { disp 179 drivers/video/of_display_timing.c disp->num_timings = of_get_child_count(timings_np); disp 180 drivers/video/of_display_timing.c if (disp->num_timings == 0) { disp 186 drivers/video/of_display_timing.c disp->timings = kcalloc(disp->num_timings, disp 189 drivers/video/of_display_timing.c if (!disp->timings) { disp 194 drivers/video/of_display_timing.c disp->num_timings = 0; disp 195 drivers/video/of_display_timing.c disp->native_mode = 0; disp 215 drivers/video/of_display_timing.c np, disp->num_timings + 1); disp 221 drivers/video/of_display_timing.c disp->native_mode = disp->num_timings; disp 223 drivers/video/of_display_timing.c disp->timings[disp->num_timings] = dt; disp 224 drivers/video/of_display_timing.c disp->num_timings++; disp 234 drivers/video/of_display_timing.c np, disp->num_timings, disp 235 drivers/video/of_display_timing.c disp->native_mode + 1); disp 237 drivers/video/of_display_timing.c return disp; disp 241 drivers/video/of_display_timing.c display_timings_release(disp); disp 242 drivers/video/of_display_timing.c disp = NULL; disp 244 drivers/video/of_display_timing.c kfree(disp); disp 33 drivers/video/of_videomode.c struct display_timings *disp; disp 36 drivers/video/of_videomode.c disp = of_get_display_timings(np); disp 37 drivers/video/of_videomode.c if (!disp) { disp 43 drivers/video/of_videomode.c index = disp->native_mode; disp 45 drivers/video/of_videomode.c ret = videomode_from_timings(disp, vm, index); disp 47 drivers/video/of_videomode.c display_timings_release(disp); disp 31 drivers/video/videomode.c int videomode_from_timings(const struct display_timings *disp, disp 36 drivers/video/videomode.c dt = display_timings_get(disp, index); disp 1022 fs/binfmt_elf_fdpic.c unsigned long maddr, disp, excess, excess1; disp 1082 fs/binfmt_elf_fdpic.c disp = phdr->p_vaddr & ~PAGE_MASK; disp 1083 fs/binfmt_elf_fdpic.c maddr = vm_mmap(file, maddr, phdr->p_memsz + disp, prot, flags, disp 1084 fs/binfmt_elf_fdpic.c phdr->p_offset - disp); disp 1087 fs/binfmt_elf_fdpic.c loop, phdr->p_memsz + disp, prot, flags, disp 1088 fs/binfmt_elf_fdpic.c phdr->p_offset - disp, maddr); disp 1095 fs/binfmt_elf_fdpic.c load_addr += PAGE_ALIGN(phdr->p_memsz + disp); disp 1097 fs/binfmt_elf_fdpic.c seg->addr = maddr + disp; disp 1107 fs/binfmt_elf_fdpic.c if (prot & PROT_WRITE && disp > 0) { disp 1108 fs/binfmt_elf_fdpic.c kdebug("clear[%d] ad=%lx sz=%lx", loop, maddr, disp); disp 1109 fs/binfmt_elf_fdpic.c if (clear_user((void __user *) maddr, disp)) disp 1111 fs/binfmt_elf_fdpic.c maddr += disp; disp 131 include/linux/dma/ipu-dma.h enum display_port disp; disp 94 include/video/display_timing.h display_timings *disp, disp 97 include/video/display_timing.h if (disp->num_timings > index) disp 98 include/video/display_timing.h return disp->timings[index]; disp 103 include/video/display_timing.h void display_timings_release(struct display_timings *disp); disp 298 include/video/imx-ipu-v3.h struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); disp 54 include/video/videomode.h int videomode_from_timings(const struct display_timings *disp, disp 663 kernel/relay.c struct rchan_percpu_buf_dispatcher disp; disp 718 kernel/relay.c disp.buf = buf; disp 719 kernel/relay.c disp.dentry = dentry; disp 724 kernel/relay.c &disp, 1); disp 53 scripts/dtc/fdtget.c static int show_data(struct display_info *disp, const char *data, int len) disp 66 scripts/dtc/fdtget.c is_string = (disp->type) == 's' || disp 67 scripts/dtc/fdtget.c (!disp->type && util_is_printable_string(data, len)); disp 80 scripts/dtc/fdtget.c size = disp->size; disp 89 scripts/dtc/fdtget.c fmt[1] = disp->type ? disp->type : 'd'; disp 192 scripts/dtc/fdtget.c static int show_data_for_item(const void *blob, struct display_info *disp, disp 198 scripts/dtc/fdtget.c switch (disp->mode) { disp 211 scripts/dtc/fdtget.c if (show_data(disp, value, len)) disp 215 scripts/dtc/fdtget.c } else if (disp->default_val) { disp 216 scripts/dtc/fdtget.c puts(disp->default_val); disp 236 scripts/dtc/fdtget.c static int do_fdtget(struct display_info *disp, const char *filename, disp 250 scripts/dtc/fdtget.c if (disp->default_val) { disp 251 scripts/dtc/fdtget.c puts(disp->default_val); disp 260 scripts/dtc/fdtget.c if (show_data_for_item(blob, disp, node, prop)) disp 294 scripts/dtc/fdtget.c struct display_info disp; disp 298 scripts/dtc/fdtget.c memset(&disp, '\0', sizeof(disp)); disp 299 scripts/dtc/fdtget.c disp.size = -1; disp 300 scripts/dtc/fdtget.c disp.mode = MODE_SHOW_VALUE; disp 312 scripts/dtc/fdtget.c if (utilfdt_decode_type(optarg, &disp.type, disp 313 scripts/dtc/fdtget.c &disp.size)) disp 318 scripts/dtc/fdtget.c disp.mode = MODE_LIST_PROPS; disp 323 scripts/dtc/fdtget.c disp.mode = MODE_LIST_SUBNODES; disp 328 scripts/dtc/fdtget.c disp.default_val = optarg; disp 349 scripts/dtc/fdtget.c if (do_fdtget(&disp, filename, argv, argc, args_per_step)) disp 56 scripts/dtc/fdtput.c static int encode_value(struct display_info *disp, char **arg, int arg_count, disp 69 scripts/dtc/fdtput.c if (disp->verbose) disp 73 scripts/dtc/fdtput.c fmt[1] = disp->type ? disp->type : 'd'; disp 77 scripts/dtc/fdtput.c if (disp->type == 's') disp 80 scripts/dtc/fdtput.c len = disp->size == -1 ? 4 : disp->size; disp 94 scripts/dtc/fdtput.c if (disp->type == 's') { disp 96 scripts/dtc/fdtput.c if (disp->verbose) disp 105 scripts/dtc/fdtput.c if (disp->verbose) { disp 107 scripts/dtc/fdtput.c disp->size == 1 ? "byte" : disp 108 scripts/dtc/fdtput.c disp->size == 2 ? "short" : "int", disp 115 scripts/dtc/fdtput.c if (disp->verbose) disp 221 scripts/dtc/fdtput.c static int do_fdtput(struct display_info *disp, const char *filename, disp 232 scripts/dtc/fdtput.c switch (disp->oper) { disp 239 scripts/dtc/fdtput.c if (disp->auto_path && create_paths(blob, *arg)) disp 241 scripts/dtc/fdtput.c if (encode_value(disp, arg + 2, arg_count - 2, &value, &len) || disp 247 scripts/dtc/fdtput.c if (disp->auto_path) disp 288 scripts/dtc/fdtput.c struct display_info disp; disp 291 scripts/dtc/fdtput.c memset(&disp, '\0', sizeof(disp)); disp 292 scripts/dtc/fdtput.c disp.size = -1; disp 293 scripts/dtc/fdtput.c disp.oper = OPER_WRITE_PROP; disp 310 scripts/dtc/fdtput.c disp.oper = OPER_CREATE_NODE; disp 316 scripts/dtc/fdtput.c disp.auto_path = 1; disp 319 scripts/dtc/fdtput.c if (utilfdt_decode_type(optarg, &disp.type, disp 320 scripts/dtc/fdtput.c &disp.size)) disp 325 scripts/dtc/fdtput.c disp.verbose = 1; disp 338 scripts/dtc/fdtput.c if (disp.oper == OPER_WRITE_PROP) { disp 345 scripts/dtc/fdtput.c if (do_fdtput(&disp, filename, argv, argc))