disabled_rb_mask 3151 drivers/gpu/drm/radeon/evergreen.c 	u32 disabled_rb_mask;
disabled_rb_mask 3473 drivers/gpu/drm/radeon/evergreen.c 	disabled_rb_mask = tmp;
disabled_rb_mask 3478 drivers/gpu/drm/radeon/evergreen.c 	if ((disabled_rb_mask & tmp) == tmp) {
disabled_rb_mask 3480 drivers/gpu/drm/radeon/evergreen.c 			disabled_rb_mask &= ~(1 << i);
disabled_rb_mask 3508 drivers/gpu/drm/radeon/evergreen.c 		if ((disabled_rb_mask & 3) == 1) {
disabled_rb_mask 3518 drivers/gpu/drm/radeon/evergreen.c 						EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
disabled_rb_mask  901 drivers/gpu/drm/radeon/ni.c 	u32 disabled_rb_mask;
disabled_rb_mask 1102 drivers/gpu/drm/radeon/ni.c 	disabled_rb_mask = tmp;
disabled_rb_mask 1107 drivers/gpu/drm/radeon/ni.c 	if ((disabled_rb_mask & tmp) == tmp) {
disabled_rb_mask 1109 drivers/gpu/drm/radeon/ni.c 			disabled_rb_mask &= ~(1 << i);
disabled_rb_mask 1140 drivers/gpu/drm/radeon/ni.c 		if ((disabled_rb_mask & 3) == 2) {
disabled_rb_mask 1152 drivers/gpu/drm/radeon/ni.c 						CAYMAN_MAX_BACKENDS, disabled_rb_mask);
disabled_rb_mask 1939 drivers/gpu/drm/radeon/r600.c 			      u32 disabled_rb_mask)
disabled_rb_mask 1947 drivers/gpu/drm/radeon/r600.c 	tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
disabled_rb_mask 1950 drivers/gpu/drm/radeon/r600.c 		disabled_rb_mask = tmp;
disabled_rb_mask 1953 drivers/gpu/drm/radeon/r600.c 	req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
disabled_rb_mask 1968 drivers/gpu/drm/radeon/r600.c 		if (!(mask & disabled_rb_mask)) {
disabled_rb_mask 2003 drivers/gpu/drm/radeon/r600.c 	u32 disabled_rb_mask;
disabled_rb_mask 2125 drivers/gpu/drm/radeon/r600.c 	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
disabled_rb_mask 2130 drivers/gpu/drm/radeon/r600.c 	if ((disabled_rb_mask & tmp) == tmp) {
disabled_rb_mask 2132 drivers/gpu/drm/radeon/r600.c 			disabled_rb_mask &= ~(1 << i);
disabled_rb_mask 2136 drivers/gpu/drm/radeon/r600.c 					R6XX_MAX_BACKENDS, disabled_rb_mask);
disabled_rb_mask 1190 drivers/gpu/drm/radeon/rv770.c 	u32 disabled_rb_mask;
disabled_rb_mask 1341 drivers/gpu/drm/radeon/rv770.c 	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
disabled_rb_mask 1346 drivers/gpu/drm/radeon/rv770.c 	if ((disabled_rb_mask & tmp) == tmp) {
disabled_rb_mask 1348 drivers/gpu/drm/radeon/rv770.c 			disabled_rb_mask &= ~(1 << i);
disabled_rb_mask 1352 drivers/gpu/drm/radeon/rv770.c 					R7XX_MAX_BACKENDS, disabled_rb_mask);