direct_rd_mod_wt 97 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h static inline void mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, direct_rd_mod_wt 102 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; direct_rd_mod_wt 103 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_rd_mod_wt->mask_value = mask; direct_rd_mod_wt 104 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_rd_mod_wt->write_data = data; direct_rd_mod_wt 105 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h memcpy((void *)init_table, direct_rd_mod_wt, direct_rd_mod_wt 121 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \ direct_rd_mod_wt 770 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; direct_rd_mod_wt 778 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; direct_rd_mod_wt 210 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; direct_rd_mod_wt 217 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;