dir0_msn          174 arch/x86/kernel/cpu/cyrix.c 	unsigned char dir0, dir0_msn, dir1 = 0;
dir0_msn          177 arch/x86/kernel/cpu/cyrix.c 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
dir0_msn          179 arch/x86/kernel/cpu/cyrix.c 	switch (dir0_msn) {
dir0_msn          193 arch/x86/kernel/cpu/cyrix.c 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
dir0_msn          213 arch/x86/kernel/cpu/cyrix.c 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
dir0_msn          226 arch/x86/kernel/cpu/cyrix.c 	switch (dir0_msn) {
dir0_msn          320 arch/x86/kernel/cpu/cyrix.c 			dir0_msn++;  /* M II */
dir0_msn          339 arch/x86/kernel/cpu/cyrix.c 			dir0_msn = 0;
dir0_msn          344 arch/x86/kernel/cpu/cyrix.c 			dir0_msn = 0;
dir0_msn          351 arch/x86/kernel/cpu/cyrix.c 		dir0_msn = 7;
dir0_msn          354 arch/x86/kernel/cpu/cyrix.c 	strcpy(buf, Cx86_model[dir0_msn & 7]);