dir0               46 arch/alpha/include/asm/core_titan.h 	titan_64	dir0;
dir0               45 arch/alpha/include/asm/core_tsunami.h 	tsunami_64	dir0;
dir0              378 arch/alpha/kernel/core_titan.c 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);
dir0              401 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);
dir0              198 arch/alpha/kernel/sys_dp264.c 	pld = TSUNAMI_cchip->dir0.csr;
dir0               21 arch/x86/kernel/cpu/cyrix.c static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
dir0               36 arch/x86/kernel/cpu/cyrix.c 			*dir0 = 0xfd;
dir0               39 arch/x86/kernel/cpu/cyrix.c 			*dir0 = 0xfe;
dir0               45 arch/x86/kernel/cpu/cyrix.c 		*dir0 = getCx86(CX86_DIR0);
dir0               50 arch/x86/kernel/cpu/cyrix.c static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
dir0               55 arch/x86/kernel/cpu/cyrix.c 	__do_cyrix_devid(dir0, dir1);
dir0              174 arch/x86/kernel/cpu/cyrix.c 	unsigned char dir0, dir0_msn, dir1 = 0;
dir0              176 arch/x86/kernel/cpu/cyrix.c 	__do_cyrix_devid(&dir0, &dir1);
dir0              177 arch/x86/kernel/cpu/cyrix.c 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
dir0              193 arch/x86/kernel/cpu/cyrix.c 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
dir0              209 arch/x86/kernel/cpu/cyrix.c 	do_cyrix_devid(&dir0, &dir1);
dir0              213 arch/x86/kernel/cpu/cyrix.c 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
dir0              214 arch/x86/kernel/cpu/cyrix.c 	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
dir0              416 arch/x86/kernel/cpu/cyrix.c 		unsigned char dir0, dir1;
dir0              425 arch/x86/kernel/cpu/cyrix.c 		do_cyrix_devid(&dir0, &dir1);
dir0              427 arch/x86/kernel/cpu/cyrix.c 		dir0 >>= 4;
dir0              431 arch/x86/kernel/cpu/cyrix.c 		if (dir0 == 5 || dir0 == 3) {