dimB               88 arch/alpha/kernel/sys_dp264.c 	volatile unsigned long *dimB;
dimB               89 arch/alpha/kernel/sys_dp264.c 	if (bcpu == 0) dimB = &cchip->dim0.csr;
dimB               90 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 1) dimB = &cchip->dim1.csr;
dimB               91 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
dimB               92 arch/alpha/kernel/sys_dp264.c 	else dimB = &cchip->dim3.csr;
dimB               94 arch/alpha/kernel/sys_dp264.c 	*dimB = mask | isa_enable;
dimB               96 arch/alpha/kernel/sys_dp264.c 	*dimB;
dimB              103 arch/alpha/kernel/sys_titan.c 	volatile unsigned long *dimB;
dimB              104 arch/alpha/kernel/sys_titan.c 	dimB = &cchip->dim0.csr;
dimB              105 arch/alpha/kernel/sys_titan.c 	if (bcpu == 1) dimB = &cchip->dim1.csr;
dimB              106 arch/alpha/kernel/sys_titan.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
dimB              107 arch/alpha/kernel/sys_titan.c 	else if (bcpu == 3) dimB = &cchip->dim3.csr;
dimB              109 arch/alpha/kernel/sys_titan.c 	*dimB = mask | isa_enable;
dimB              111 arch/alpha/kernel/sys_titan.c 	*dimB;