dim2               59 arch/alpha/include/asm/core_titan.h 	titan_64	dim2;
dim2               59 arch/alpha/include/asm/core_tsunami.h 	tsunami_64	dim2;
dim2               55 arch/alpha/kernel/sys_dp264.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim2               71 arch/alpha/kernel/sys_dp264.c 	dim2 = &cchip->dim2.csr;
dim2               75 arch/alpha/kernel/sys_dp264.c 	if (!cpu_possible(2)) dim2 = &dummy;
dim2               80 arch/alpha/kernel/sys_dp264.c 	*dim2 = mask2;
dim2               85 arch/alpha/kernel/sys_dp264.c 	*dim2;
dim2               91 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
dim2               69 arch/alpha/kernel/sys_titan.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim2               86 arch/alpha/kernel/sys_titan.c 	dim2 = &cchip->dim2.csr;
dim2               90 arch/alpha/kernel/sys_titan.c 	if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
dim2               95 arch/alpha/kernel/sys_titan.c 	*dim2 = mask2;
dim2              100 arch/alpha/kernel/sys_titan.c 	*dim2;
dim2              106 arch/alpha/kernel/sys_titan.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
dim2               78 drivers/staging/most/dim2/hal.c 	struct dim2_regs __iomem *dim2; /* DIM2 core base address */
dim2              147 drivers/staging/most/dim2/hal.c 	writel(val, &g.dim2->MADR);
dim2              150 drivers/staging/most/dim2/hal.c 	while ((readl(&g.dim2->MCTL) & 1) != 1)
dim2              153 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
dim2              163 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
dim2              164 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MDAT0);
dim2              174 drivers/staging/most/dim2/hal.c 	return readl((&g.dim2->MDAT0) + mdat_idx);
dim2              181 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
dim2              184 drivers/staging/most/dim2/hal.c 		writel(value[0], &g.dim2->MDAT0);
dim2              186 drivers/staging/most/dim2/hal.c 		writel(value[1], &g.dim2->MDAT1);
dim2              188 drivers/staging/most/dim2/hal.c 		writel(value[2], &g.dim2->MDAT2);
dim2              190 drivers/staging/most/dim2/hal.c 		writel(value[3], &g.dim2->MDAT3);
dim2              192 drivers/staging/most/dim2/hal.c 	writel(mask[0], &g.dim2->MDWE0);
dim2              193 drivers/staging/most/dim2/hal.c 	writel(mask[1], &g.dim2->MDWE1);
dim2              194 drivers/staging/most/dim2/hal.c 	writel(mask[2], &g.dim2->MDWE2);
dim2              195 drivers/staging/most/dim2/hal.c 	writel(mask[3], &g.dim2->MDWE3);
dim2              360 drivers/staging/most/dim2/hal.c 	writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
dim2              366 drivers/staging/most/dim2/hal.c 	writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
dim2              375 drivers/staging/most/dim2/hal.c 	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
dim2              519 drivers/staging/most/dim2/hal.c 	writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
dim2              524 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MIEN);
dim2              527 drivers/staging/most/dim2/hal.c 	writel(0xFFFFFFFF, &g.dim2->ACSR0);
dim2              528 drivers/staging/most/dim2/hal.c 	writel(0xFFFFFFFF, &g.dim2->ACSR1);
dim2              531 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->ACMR0);
dim2              532 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->ACMR1);
dim2              544 drivers/staging/most/dim2/hal.c 	       &g.dim2->MLBC0);
dim2              547 drivers/staging/most/dim2/hal.c 	writel(0xFFFFFFFF, &g.dim2->HCMR0);
dim2              548 drivers/staging/most/dim2/hal.c 	writel(0xFFFFFFFF, &g.dim2->HCMR1);
dim2              551 drivers/staging/most/dim2/hal.c 	writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
dim2              555 drivers/staging/most/dim2/hal.c 	       true << ACTL_SCE_BIT, &g.dim2->ACTL);
dim2              563 drivers/staging/most/dim2/hal.c 	u32 const c1 = readl(&g.dim2->MLBC1);
dim2              566 drivers/staging/most/dim2/hal.c 	writel(c1 & nda_mask, &g.dim2->MLBC1);
dim2              567 drivers/staging/most/dim2/hal.c 	return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
dim2              568 drivers/staging/most/dim2/hal.c 	       (readl(&g.dim2->MLBC0) & mask0) != 0;
dim2              591 drivers/staging/most/dim2/hal.c 	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
dim2              729 drivers/staging/most/dim2/hal.c 	g.dim2 = dim_base_address;
dim2              777 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MS0);
dim2              778 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MS1);
dim2              825 drivers/staging/most/dim2/hal.c 		writel(bit_mask(20), &g.dim2->MIEN);
dim2              892 drivers/staging/most/dim2/hal.c 		writel(0, &g.dim2->MIEN);