dim1               45 arch/alpha/include/asm/core_titan.h 	titan_64	dim1;
dim1               44 arch/alpha/include/asm/core_tsunami.h 	tsunami_64	dim1;
dim1              377 arch/alpha/kernel/core_titan.c 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);
dim1              400 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);
dim1               55 arch/alpha/kernel/sys_dp264.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim1               70 arch/alpha/kernel/sys_dp264.c 	dim1 = &cchip->dim1.csr;
dim1               74 arch/alpha/kernel/sys_dp264.c 	if (!cpu_possible(1)) dim1 = &dummy;
dim1               79 arch/alpha/kernel/sys_dp264.c 	*dim1 = mask1;
dim1               84 arch/alpha/kernel/sys_dp264.c 	*dim1;
dim1               90 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 1) dimB = &cchip->dim1.csr;
dim1               69 arch/alpha/kernel/sys_titan.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim1               85 arch/alpha/kernel/sys_titan.c 	dim1 = &cchip->dim1.csr;
dim1               89 arch/alpha/kernel/sys_titan.c 	if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
dim1               94 arch/alpha/kernel/sys_titan.c 	*dim1 = mask1;
dim1               99 arch/alpha/kernel/sys_titan.c 	*dim1;
dim1              105 arch/alpha/kernel/sys_titan.c 	if (bcpu == 1) dimB = &cchip->dim1.csr;