dim0               44 arch/alpha/include/asm/core_titan.h 	titan_64	dim0;
dim0               43 arch/alpha/include/asm/core_tsunami.h 	tsunami_64	dim0;
dim0              376 arch/alpha/kernel/core_titan.c 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);
dim0              399 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);
dim0               55 arch/alpha/kernel/sys_dp264.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim0               69 arch/alpha/kernel/sys_dp264.c 	dim0 = &cchip->dim0.csr;
dim0               73 arch/alpha/kernel/sys_dp264.c 	if (!cpu_possible(0)) dim0 = &dummy;
dim0               78 arch/alpha/kernel/sys_dp264.c 	*dim0 = mask0;
dim0               83 arch/alpha/kernel/sys_dp264.c 	*dim0;
dim0               89 arch/alpha/kernel/sys_dp264.c 	if (bcpu == 0) dimB = &cchip->dim0.csr;
dim0               69 arch/alpha/kernel/sys_titan.c 	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
dim0               84 arch/alpha/kernel/sys_titan.c 	dim0 = &cchip->dim0.csr;
dim0               88 arch/alpha/kernel/sys_titan.c 	if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
dim0               93 arch/alpha/kernel/sys_titan.c 	*dim0 = mask0;
dim0               98 arch/alpha/kernel/sys_titan.c 	*dim0;
dim0              104 arch/alpha/kernel/sys_titan.c 	dimB = &cchip->dim0.csr;