dig_fe 244 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c masterCmdData2.bits.dig_fe = psr_context->engineId; dig_fe 657 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c masterCmdData2.bits.dig_fe = psr_context->engineId; dig_fe 221 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h unsigned int dig_fe:3; /*[2:0]*/ dig_fe 2568 drivers/gpu/drm/radeon/evergreen.c unsigned dig_fe; dig_fe 2580 drivers/gpu/drm/radeon/evergreen.c dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); dig_fe 2581 drivers/gpu/drm/radeon/evergreen.c if (dig_fe & NI_DIG_FE_CNTL_SYMCLK_FE_ON && dig_fe 2582 drivers/gpu/drm/radeon/evergreen.c crtc_id == NI_DIG_FE_CNTL_SOURCE_SELECT(dig_fe)) { dig_fe 2586 drivers/gpu/drm/radeon/evergreen.c dig_fe = i; dig_fe 2610 drivers/gpu/drm/radeon/evergreen.c *ret_dig_fe = dig_fe; dig_fe 2625 drivers/gpu/drm/radeon/evergreen.c unsigned dig_fe) dig_fe 2631 drivers/gpu/drm/radeon/evergreen.c if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) { dig_fe 2632 drivers/gpu/drm/radeon/evergreen.c DRM_ERROR("invalid dig_fe %d\n", dig_fe); dig_fe 2637 drivers/gpu/drm/radeon/evergreen.c evergreen_dp_offsets[dig_fe]); dig_fe 2639 drivers/gpu/drm/radeon/evergreen.c DRM_ERROR("dig %d , should be enable\n", dig_fe); dig_fe 2645 drivers/gpu/drm/radeon/evergreen.c evergreen_dp_offsets[dig_fe], stream_ctrl); dig_fe 2648 drivers/gpu/drm/radeon/evergreen.c evergreen_dp_offsets[dig_fe]); dig_fe 2653 drivers/gpu/drm/radeon/evergreen.c evergreen_dp_offsets[dig_fe]); dig_fe 2658 drivers/gpu/drm/radeon/evergreen.c fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); dig_fe 2660 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); dig_fe 2668 drivers/gpu/drm/radeon/evergreen.c unsigned dig_fe; dig_fe 2716 drivers/gpu/drm/radeon/evergreen.c evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe)) dig_fe 2717 drivers/gpu/drm/radeon/evergreen.c evergreen_blank_dp_output(rdev, dig_fe);