didt_block_info 854 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; didt_block_info 859 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info &= ~SQ_Enable_MASK; didt_block_info 860 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info |= en << SQ_Enable_SHIFT; didt_block_info 866 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info &= ~DB_Enable_MASK; didt_block_info 867 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info |= en << DB_Enable_SHIFT; didt_block_info 873 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info &= ~TD_Enable_MASK; didt_block_info 874 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info |= en << TD_Enable_SHIFT; didt_block_info 880 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info &= ~TCP_Enable_MASK; didt_block_info 881 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c didt_block_info |= en << TCP_Enable_SHIFT; didt_block_info 928 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);