dhar              878 drivers/edac/amd64_edac.c 		 pvt->dhar, dhar_base(pvt));
dhar              898 drivers/edac/amd64_edac.c 		 pvt->dhar, dhar_base(pvt),
dhar             2789 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);
dhar             2821 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
dhar              148 drivers/edac/amd64_edac.h #define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
dhar              149 drivers/edac/amd64_edac.h #define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
dhar              150 drivers/edac/amd64_edac.h #define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)
dhar              153 drivers/edac/amd64_edac.h #define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)
dhar              359 drivers/edac/amd64_edac.h 	u32 dhar;		/* DRAM Hoist reg */
dhar              530 drivers/edac/amd64_edac.h 	return (pvt)->dhar & BIT(0);
dhar               14 drivers/edac/amd64_edac_dbg.c EDAC_DCT_ATTR_SHOW(dhar);
dhar               38 drivers/edac/amd64_edac_dbg.c static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);