dh_data           198 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	struct dchub_init_data *dh_data)
dh_data           201 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	switch (dh_data->fb_mode) {
dh_data           209 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
dh_data           212 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
dh_data           215 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
dh_data           220 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
dh_data           223 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
dh_data           226 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
dh_data           243 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	dh_data->dchub_initialzied = true;
dh_data           244 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	dh_data->dchub_info_valid = false;
dh_data           634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	struct dchub_init_data *dh_data)
dh_data           644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	switch (dh_data->fb_mode) {
dh_data           654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
dh_data           657 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
dh_data           660 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data           661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 						dh_data->zfb_size_in_byte - 1) >> 22);
dh_data           667 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
dh_data           670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
dh_data           673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data           674 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 						dh_data->zfb_size_in_byte - 1) >> 22);
dh_data           691 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	dh_data->dchub_initialzied = true;
dh_data           692 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	dh_data->dchub_info_valid = false;
dh_data           312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 	struct dchub_init_data *dh_data);
dh_data          2946 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
dh_data          2951 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubbub->funcs->update_dchub(hubbub, dh_data);
dh_data           402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		struct dchub_init_data *dh_data)
dh_data           409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	switch (dh_data->fb_mode) {
dh_data           420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
dh_data           425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
dh_data           430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data           431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 						dh_data->zfb_size_in_byte - 1) >> 24);
dh_data           438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
dh_data           443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
dh_data           448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 				AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data           449 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 						dh_data->zfb_size_in_byte - 1) >> 24);
dh_data           472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	dh_data->dchub_initialzied = true;
dh_data           473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	dh_data->dchub_info_valid = false;
dh_data           116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 		struct dchub_init_data *dh_data);
dh_data           108 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 			struct dchub_init_data *dh_data);
dh_data           164 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h 				struct dchub_init_data *dh_data);
dh_data           136 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 		struct dchub_init_data *dh_data);