DWB_SOURCE_SELECT  169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t DWB_SOURCE_SELECT;
DWB_SOURCE_SELECT  310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(DWB_SOURCE_SELECT,
DWB_SOURCE_SELECT  313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(DWB_SOURCE_SELECT,
DWB_SOURCE_SELECT   43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SR(DWB_SOURCE_SELECT),\
DWB_SOURCE_SELECT   74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
DWB_SOURCE_SELECT   75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\