DVMM_PTE_CONTROL  153 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE_3(DVMM_PTE_CONTROL,
DVMM_PTE_CONTROL   58 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DVMM_PTE_CONTROL, DCP, id),\
DVMM_PTE_CONTROL   97 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	uint32_t DVMM_PTE_CONTROL;
DVMM_PTE_CONTROL  169 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
DVMM_PTE_CONTROL  170 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
DVMM_PTE_CONTROL  171 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
DVMM_PTE_CONTROL  130 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		DVMM_PTE_CONTROL,
DVMM_PTE_CONTROL  136 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		DVMM_PTE_CONTROL,
DVMM_PTE_CONTROL  142 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		DVMM_PTE_CONTROL,