dev_clk 174 drivers/clk/actions/owl-s500.c static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); dev_clk 386 drivers/clk/actions/owl-s500.c &dev_clk.common, dev_clk 443 drivers/clk/actions/owl-s500.c [CLK_DEV] = &dev_clk.common.hw, dev_clk 115 drivers/clk/actions/owl-s900.c static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); dev_clk 512 drivers/clk/actions/owl-s900.c &dev_clk.common, dev_clk 605 drivers/clk/actions/owl-s900.c [CLK_DEV] = &dev_clk.common.hw, dev_clk 227 drivers/clk/clk-vt8500.c struct clk_device *dev_clk; dev_clk 237 drivers/clk/clk-vt8500.c dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL); dev_clk 238 drivers/clk/clk-vt8500.c if (WARN_ON(!dev_clk)) dev_clk 241 drivers/clk/clk-vt8500.c dev_clk->lock = &_lock; dev_clk 245 drivers/clk/clk-vt8500.c dev_clk->en_reg = pmc_base + en_reg; dev_clk 246 drivers/clk/clk-vt8500.c rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit); dev_clk 257 drivers/clk/clk-vt8500.c dev_clk->div_reg = pmc_base + div_reg; dev_clk 262 drivers/clk/clk-vt8500.c dev_clk->div_mask = 0x1f; dev_clk 264 drivers/clk/clk-vt8500.c of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); dev_clk 283 drivers/clk/clk-vt8500.c kfree(dev_clk); dev_clk 293 drivers/clk/clk-vt8500.c dev_clk->hw.init = &init; dev_clk 295 drivers/clk/clk-vt8500.c hw = &dev_clk->hw; dev_clk 298 drivers/clk/clk-vt8500.c kfree(dev_clk); dev_clk 2251 drivers/dma/xilinx/xilinx_dma.c struct clk **dev_clk, struct clk **tmp_clk, dev_clk 2267 drivers/dma/xilinx/xilinx_dma.c *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); dev_clk 2268 drivers/dma/xilinx/xilinx_dma.c if (IS_ERR(*dev_clk)) { dev_clk 2269 drivers/dma/xilinx/xilinx_dma.c err = PTR_ERR(*dev_clk); dev_clk 2280 drivers/dma/xilinx/xilinx_dma.c err = clk_prepare_enable(*dev_clk);