DTLB              169 arch/arc/include/asm/perf_event.h 	[C(DTLB)] = {
DTLB              109 arch/arm/kernel/perf_event_v6.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV6_PERFCTR_DTLB_MISS,
DTLB              110 arch/arm/kernel/perf_event_v6.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV6_PERFCTR_DTLB_MISS,
DTLB              172 arch/arm/kernel/perf_event_v6.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV6MPCORE_PERFCTR_DTLB_MISS,
DTLB              173 arch/arm/kernel/perf_event_v6.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV6MPCORE_PERFCTR_DTLB_MISS,
DTLB              192 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              193 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              236 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              237 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              282 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              283 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              331 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
DTLB              332 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
DTLB              380 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              381 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              429 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              430 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
DTLB              431 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)]	= ARMV7_A12_PERFCTR_PF_TLB_REFILL,
DTLB              480 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	= KRAIT_PERFCTR_L1_DTLB_ACCESS,
DTLB              481 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)]	= KRAIT_PERFCTR_L1_DTLB_ACCESS,
DTLB              523 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
DTLB              524 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
DTLB              525 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
DTLB              526 arch/arm/kernel/perf_event_v7.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
DTLB               80 arch/arm/kernel/perf_event_xscale.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= XSCALE_PERFCTR_DTLB_MISS,
DTLB               81 arch/arm/kernel/perf_event_xscale.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= XSCALE_PERFCTR_DTLB_MISS,
DTLB               63 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
DTLB               64 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1D_TLB,
DTLB               94 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
DTLB               95 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
DTLB              125 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
DTLB              126 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
DTLB              127 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
DTLB              128 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
DTLB              141 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
DTLB              142 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
DTLB              143 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
DTLB              144 arch/arm64/kernel/perf_event.c 	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
DTLB              802 arch/csky/kernel/perf_event.c 	[C(DTLB)] = {
DTLB              918 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = {
DTLB             1047 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = {
DTLB             1093 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = {
DTLB             1203 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = {
DTLB             1252 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = {
DTLB              304 arch/nds32/include/asm/pmu.h 	[C(DTLB)] = {
DTLB               25 arch/powerpc/perf/8xx-pmu.c #define DTLB_LOAD_MISS	(C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
DTLB               66 arch/powerpc/perf/e500-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB               65 arch/powerpc/perf/e6500-pmu.c 	[C(DTLB)] = {
DTLB              147 arch/powerpc/perf/generic-compat-pmu.c 	[ C(DTLB) ] = {
DTLB              373 arch/powerpc/perf/mpc7450-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB              637 arch/powerpc/perf/power5+-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB              579 arch/powerpc/perf/power5-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB              500 arch/powerpc/perf/power6-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB              351 arch/powerpc/perf/power7-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB              299 arch/powerpc/perf/power8-pmu.c 	[ C(DTLB) ] = {
DTLB              356 arch/powerpc/perf/power9-pmu.c 	[ C(DTLB) ] = {
DTLB              451 arch/powerpc/perf/ppc970-pmu.c 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
DTLB               98 arch/riscv/kernel/perf_event.c 	[C(DTLB)] = {
DTLB              136 arch/sh/kernel/cpu/sh4/perf_event.c 	[ C(DTLB) ] = {
DTLB              161 arch/sh/kernel/cpu/sh4a/perf_event.c 	[ C(DTLB) ] = {
DTLB              263 arch/sparc/kernel/perf_event.c [C(DTLB)] = {
DTLB              401 arch/sparc/kernel/perf_event.c [C(DTLB)] = {
DTLB              536 arch/sparc/kernel/perf_event.c [C(DTLB)] = {
DTLB              673 arch/sparc/kernel/perf_event.c [C(DTLB)] = {
DTLB               64 arch/x86/events/amd/core.c  [ C(DTLB) ] = {
DTLB              168 arch/x86/events/amd/core.c [C(DTLB)] = {
DTLB              467 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB              701 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB              851 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1013 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1196 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1301 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1392 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1548 arch/x86/events/intel/core.c  [ C(DTLB) ] = {
DTLB             1677 arch/x86/events/intel/core.c 	[C(DTLB)] = {
DTLB             1793 arch/x86/events/intel/core.c 	[C(DTLB)] = {
DTLB             4852 arch/x86/events/intel/core.c 		hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
DTLB               73 arch/x86/events/intel/knc.c  [ C(DTLB) ] = {
DTLB              533 arch/x86/events/intel/p4.c  [ C(DTLB) ] = {
DTLB               70 arch/x86/events/intel/p6.c  [ C(DTLB) ] = {
DTLB               90 arch/xtensa/kernel/perf_event.c 	[C(DTLB)] = {
DTLB              528 tools/perf/util/evsel.c  [C(DTLB)]	= (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH),