AUX_DPHY_RX_CONTROL0  504 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
AUX_DPHY_RX_CONTROL0  509 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
AUX_DPHY_RX_CONTROL0   41 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
AUX_DPHY_RX_CONTROL0  109 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t AUX_DPHY_RX_CONTROL0;
AUX_DPHY_RX_CONTROL0 1398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
AUX_DPHY_RX_CONTROL0   37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
AUX_DPHY_RX_CONTROL0   74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t AUX_DPHY_RX_CONTROL0;
AUX_DPHY_RX_CONTROL0  301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);