DSC_TOP_CONTROL   158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
DSC_TOP_CONTROL   229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_UPDATE(DSC_TOP_CONTROL,
DSC_TOP_CONTROL   247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_UPDATE(DSC_TOP_CONTROL,
DSC_TOP_CONTROL    36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
DSC_TOP_CONTROL   461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	uint32_t DSC_TOP_CONTROL;