DSCL_MEM_PWR_CTRL   86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(DSCL_MEM_PWR_CTRL,
DSCL_MEM_PWR_CTRL  167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
DSCL_MEM_PWR_CTRL  620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	uint32_t DSCL_MEM_PWR_CTRL