DSCL               52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
DSCL               53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
DSCL               54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(OTG_H_BLANK, DSCL, id), \
DSCL               55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(OTG_V_BLANK, DSCL, id), \
DSCL               56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_MODE, DSCL, id), \
DSCL               57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(LB_DATA_FORMAT, DSCL, id), \
DSCL               58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(LB_MEMORY_CTRL, DSCL, id), \
DSCL               59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_AUTOCAL, DSCL, id), \
DSCL               60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_BLACK_OFFSET, DSCL, id), \
DSCL               61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_TAP_CONTROL, DSCL, id), \
DSCL               62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
DSCL               63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
DSCL               64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_2TAP_CONTROL, DSCL, id), \
DSCL               65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(MPC_SIZE, DSCL, id), \
DSCL               66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
DSCL               67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
DSCL               68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
DSCL               69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
DSCL               70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
DSCL               71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
DSCL               72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
DSCL               73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
DSCL               74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
DSCL               75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
DSCL               76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(RECOUT_START, DSCL, id), \
DSCL               77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(RECOUT_SIZE, DSCL, id), \
DSCL              166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
DSCL              167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)