dep_sclk_table 761 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; dep_sclk_table 767 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table = table_info->vdd_dep_on_sclk; dep_sclk_table 770 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, dep_sclk_table 773 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, dep_sclk_table 786 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < dep_sclk_table->count; i++) { dep_sclk_table 788 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table->entries[i].clk) { dep_sclk_table 791 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table->entries[i].clk; dep_sclk_table 799 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; dep_sclk_table 827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; dep_sclk_table 834 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table = table_info->vdd_dep_on_sclk; dep_sclk_table 843 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c entries[i].vddc = dep_sclk_table->entries[i].vddc; dep_sclk_table 846 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, dep_sclk_table 867 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; dep_sclk_table 876 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table = table_info->vdd_dep_on_sclk; dep_sclk_table 881 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c || min_vddc > dep_sclk_table->entries[0].vddc) dep_sclk_table 882 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c min_vddc = dep_sclk_table->entries[0].vddc; dep_sclk_table 885 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) dep_sclk_table 886 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; dep_sclk_table 4655 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; dep_sclk_table 4662 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dep_sclk_table = table_info->vdd_dep_on_sclk; dep_sclk_table 4663 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < dep_sclk_table->count; i++) dep_sclk_table 4664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; dep_sclk_table 4665 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = dep_sclk_table->count;