dep_on_mclk      1757 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
dep_on_mclk      1764 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
dep_on_mclk      1767 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		dep_on_mclk = table_info->vdd_dep_on_mclk;
dep_on_mclk      1769 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(dep_on_mclk,
dep_on_mclk      1776 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		for (i = 0; i < dep_on_mclk->count; i++) {
dep_on_mclk      1777 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			if (dep_on_mclk->entries[i].clk == mem_clock)
dep_on_mclk      1780 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
dep_on_mclk      1791 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
dep_on_mclk      1793 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(uint8_t)(dep_on_mclk->entries[i].vddInd);