denali 40 drivers/mtd/nand/raw/denali.c #define DENALI_BANK(denali) ((denali)->active_bank << 24) denali 60 drivers/mtd/nand/raw/denali.c static u32 denali_direct_read(struct denali_controller *denali, u32 addr) denali 62 drivers/mtd/nand/raw/denali.c return ioread32(denali->host + addr); denali 65 drivers/mtd/nand/raw/denali.c static void denali_direct_write(struct denali_controller *denali, u32 addr, denali 68 drivers/mtd/nand/raw/denali.c iowrite32(data, denali->host + addr); denali 77 drivers/mtd/nand/raw/denali.c static u32 denali_indexed_read(struct denali_controller *denali, u32 addr) denali 79 drivers/mtd/nand/raw/denali.c iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); denali 80 drivers/mtd/nand/raw/denali.c return ioread32(denali->host + DENALI_INDEXED_DATA); denali 83 drivers/mtd/nand/raw/denali.c static void denali_indexed_write(struct denali_controller *denali, u32 addr, denali 86 drivers/mtd/nand/raw/denali.c iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); denali 87 drivers/mtd/nand/raw/denali.c iowrite32(data, denali->host + DENALI_INDEXED_DATA); denali 90 drivers/mtd/nand/raw/denali.c static void denali_enable_irq(struct denali_controller *denali) denali 94 drivers/mtd/nand/raw/denali.c for (i = 0; i < denali->nbanks; i++) denali 95 drivers/mtd/nand/raw/denali.c iowrite32(U32_MAX, denali->reg + INTR_EN(i)); denali 96 drivers/mtd/nand/raw/denali.c iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); denali 99 drivers/mtd/nand/raw/denali.c static void denali_disable_irq(struct denali_controller *denali) denali 103 drivers/mtd/nand/raw/denali.c for (i = 0; i < denali->nbanks; i++) denali 104 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + INTR_EN(i)); denali 105 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); denali 108 drivers/mtd/nand/raw/denali.c static void denali_clear_irq(struct denali_controller *denali, denali 112 drivers/mtd/nand/raw/denali.c iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); denali 115 drivers/mtd/nand/raw/denali.c static void denali_clear_irq_all(struct denali_controller *denali) denali 119 drivers/mtd/nand/raw/denali.c for (i = 0; i < denali->nbanks; i++) denali 120 drivers/mtd/nand/raw/denali.c denali_clear_irq(denali, i, U32_MAX); denali 125 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = dev_id; denali 130 drivers/mtd/nand/raw/denali.c spin_lock(&denali->irq_lock); denali 132 drivers/mtd/nand/raw/denali.c for (i = 0; i < denali->nbanks; i++) { denali 133 drivers/mtd/nand/raw/denali.c irq_status = ioread32(denali->reg + INTR_STATUS(i)); denali 137 drivers/mtd/nand/raw/denali.c denali_clear_irq(denali, i, irq_status); denali 139 drivers/mtd/nand/raw/denali.c if (i != denali->active_bank) denali 142 drivers/mtd/nand/raw/denali.c denali->irq_status |= irq_status; denali 144 drivers/mtd/nand/raw/denali.c if (denali->irq_status & denali->irq_mask) denali 145 drivers/mtd/nand/raw/denali.c complete(&denali->complete); denali 148 drivers/mtd/nand/raw/denali.c spin_unlock(&denali->irq_lock); denali 153 drivers/mtd/nand/raw/denali.c static void denali_reset_irq(struct denali_controller *denali) denali 157 drivers/mtd/nand/raw/denali.c spin_lock_irqsave(&denali->irq_lock, flags); denali 158 drivers/mtd/nand/raw/denali.c denali->irq_status = 0; denali 159 drivers/mtd/nand/raw/denali.c denali->irq_mask = 0; denali 160 drivers/mtd/nand/raw/denali.c spin_unlock_irqrestore(&denali->irq_lock, flags); denali 163 drivers/mtd/nand/raw/denali.c static u32 denali_wait_for_irq(struct denali_controller *denali, u32 irq_mask) denali 168 drivers/mtd/nand/raw/denali.c spin_lock_irqsave(&denali->irq_lock, flags); denali 170 drivers/mtd/nand/raw/denali.c irq_status = denali->irq_status; denali 174 drivers/mtd/nand/raw/denali.c spin_unlock_irqrestore(&denali->irq_lock, flags); denali 178 drivers/mtd/nand/raw/denali.c denali->irq_mask = irq_mask; denali 179 drivers/mtd/nand/raw/denali.c reinit_completion(&denali->complete); denali 180 drivers/mtd/nand/raw/denali.c spin_unlock_irqrestore(&denali->irq_lock, flags); denali 182 drivers/mtd/nand/raw/denali.c time_left = wait_for_completion_timeout(&denali->complete, denali 185 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", denali 190 drivers/mtd/nand/raw/denali.c return denali->irq_status; denali 195 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 199 drivers/mtd/nand/raw/denali.c denali->active_bank = sel->bank; denali 202 drivers/mtd/nand/raw/denali.c denali->reg + PAGES_PER_BLOCK); denali 204 drivers/mtd/nand/raw/denali.c denali->reg + DEVICE_WIDTH); denali 205 drivers/mtd/nand/raw/denali.c iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); denali 206 drivers/mtd/nand/raw/denali.c iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); denali 209 drivers/mtd/nand/raw/denali.c denali->reg + TWO_ROW_ADDR_CYCLES); denali 212 drivers/mtd/nand/raw/denali.c denali->reg + ECC_CORRECTION); denali 213 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); denali 214 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); denali 215 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); denali 221 drivers/mtd/nand/raw/denali.c iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); denali 223 drivers/mtd/nand/raw/denali.c denali->reg + TCWAW_AND_ADDR_2_DATA); denali 224 drivers/mtd/nand/raw/denali.c iowrite32(sel->re_2_we, denali->reg + RE_2_WE); denali 225 drivers/mtd/nand/raw/denali.c iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); denali 226 drivers/mtd/nand/raw/denali.c iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); denali 227 drivers/mtd/nand/raw/denali.c iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); denali 228 drivers/mtd/nand/raw/denali.c iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); denali 229 drivers/mtd/nand/raw/denali.c iowrite32(sel->re_2_re, denali->reg + RE_2_RE); denali 245 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 249 drivers/mtd/nand/raw/denali.c int oob_skip = denali->oob_skip_bytes; denali 282 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 287 drivers/mtd/nand/raw/denali.c int oob_skip = denali->oob_skip_bytes; denali 412 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 415 drivers/mtd/nand/raw/denali.c u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes; denali 442 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 444 drivers/mtd/nand/raw/denali.c int bank = denali->active_bank; denali 448 drivers/mtd/nand/raw/denali.c ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); denali 477 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 488 drivers/mtd/nand/raw/denali.c denali_reset_irq(denali); denali 491 drivers/mtd/nand/raw/denali.c err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); denali 495 drivers/mtd/nand/raw/denali.c err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); denali 523 drivers/mtd/nand/raw/denali.c denali->devs_per_cs + err_device; denali 541 drivers/mtd/nand/raw/denali.c irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); denali 548 drivers/mtd/nand/raw/denali.c static void denali_setup_dma64(struct denali_controller *denali, denali 554 drivers/mtd/nand/raw/denali.c mode = DENALI_MAP10 | DENALI_BANK(denali) | page; denali 562 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode, denali 567 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode, lower_32_bits(dma_addr)); denali 570 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode, upper_32_bits(dma_addr)); denali 573 drivers/mtd/nand/raw/denali.c static void denali_setup_dma32(struct denali_controller *denali, denali 579 drivers/mtd/nand/raw/denali.c mode = DENALI_MAP10 | DENALI_BANK(denali); denali 584 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode | page, denali 588 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); denali 591 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); denali 594 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode | 0x14000, 0x2400); denali 597 drivers/mtd/nand/raw/denali.c static int denali_pio_read(struct denali_controller *denali, u32 *buf, denali 600 drivers/mtd/nand/raw/denali.c u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; denali 604 drivers/mtd/nand/raw/denali.c if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) denali 609 drivers/mtd/nand/raw/denali.c denali_reset_irq(denali); denali 612 drivers/mtd/nand/raw/denali.c buf[i] = denali->host_read(denali, addr); denali 614 drivers/mtd/nand/raw/denali.c irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); denali 624 drivers/mtd/nand/raw/denali.c static int denali_pio_write(struct denali_controller *denali, const u32 *buf, denali 627 drivers/mtd/nand/raw/denali.c u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; denali 631 drivers/mtd/nand/raw/denali.c denali_reset_irq(denali); denali 634 drivers/mtd/nand/raw/denali.c denali->host_write(denali, addr, buf[i]); denali 636 drivers/mtd/nand/raw/denali.c irq_status = denali_wait_for_irq(denali, denali 645 drivers/mtd/nand/raw/denali.c static int denali_pio_xfer(struct denali_controller *denali, void *buf, denali 649 drivers/mtd/nand/raw/denali.c return denali_pio_write(denali, buf, size, page); denali 651 drivers/mtd/nand/raw/denali.c return denali_pio_read(denali, buf, size, page); denali 654 drivers/mtd/nand/raw/denali.c static int denali_dma_xfer(struct denali_controller *denali, void *buf, denali 662 drivers/mtd/nand/raw/denali.c dma_addr = dma_map_single(denali->dev, buf, size, dir); denali 663 drivers/mtd/nand/raw/denali.c if (dma_mapping_error(denali->dev, dma_addr)) { denali 664 drivers/mtd/nand/raw/denali.c dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); denali 665 drivers/mtd/nand/raw/denali.c return denali_pio_xfer(denali, buf, size, page, write); denali 676 drivers/mtd/nand/raw/denali.c } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { denali 684 drivers/mtd/nand/raw/denali.c iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); denali 690 drivers/mtd/nand/raw/denali.c ioread32(denali->reg + DMA_ENABLE); denali 692 drivers/mtd/nand/raw/denali.c denali_reset_irq(denali); denali 693 drivers/mtd/nand/raw/denali.c denali->setup_dma(denali, dma_addr, page, write); denali 695 drivers/mtd/nand/raw/denali.c irq_status = denali_wait_for_irq(denali, irq_mask); denali 701 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + DMA_ENABLE); denali 703 drivers/mtd/nand/raw/denali.c dma_unmap_single(denali->dev, dma_addr, size, dir); denali 714 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 718 drivers/mtd/nand/raw/denali.c if (denali->dma_avail) denali 719 drivers/mtd/nand/raw/denali.c return denali_dma_xfer(denali, buf, size, page, write); denali 721 drivers/mtd/nand/raw/denali.c return denali_pio_xfer(denali, buf, size, page, write); denali 727 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 737 drivers/mtd/nand/raw/denali.c if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) denali 768 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 782 drivers/mtd/nand/raw/denali.c t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); denali 791 drivers/mtd/nand/raw/denali.c mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); denali 804 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + ACC_CLKS); denali 813 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RE_2_WE); denali 822 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RE_2_RE); denali 836 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); denali 845 drivers/mtd/nand/raw/denali.c if (denali->revision < 0x0501) denali 851 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); denali 861 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); denali 874 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); denali 885 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + CS_SETUP_CNT); denali 904 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 909 drivers/mtd/nand/raw/denali.c oobregion->offset = denali->oob_skip_bytes; denali 919 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 924 drivers/mtd/nand/raw/denali.c oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; denali 937 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 950 drivers/mtd/nand/raw/denali.c denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); denali 956 drivers/mtd/nand/raw/denali.c if (denali->devs_per_cs == 0) { denali 957 drivers/mtd/nand/raw/denali.c denali->devs_per_cs = 1; denali 958 drivers/mtd/nand/raw/denali.c iowrite32(1, denali->reg + DEVICES_CONNECTED); denali 961 drivers/mtd/nand/raw/denali.c if (denali->devs_per_cs == 1) denali 964 drivers/mtd/nand/raw/denali.c if (denali->devs_per_cs != 2) { denali 965 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "unsupported number of devices %d\n", denali 966 drivers/mtd/nand/raw/denali.c denali->devs_per_cs); denali 985 drivers/mtd/nand/raw/denali.c denali->oob_skip_bytes <<= 1; denali 992 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 996 drivers/mtd/nand/raw/denali.c ret = nand_ecc_choose_conf(chip, denali->ecc_caps, denali 997 drivers/mtd/nand/raw/denali.c mtd->oobsize - denali->oob_skip_bytes); denali 999 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "Failed to setup ECC settings.\n"); denali 1003 drivers/mtd/nand/raw/denali.c dev_dbg(denali->dev, denali 1014 drivers/mtd/nand/raw/denali.c static void denali_exec_in8(struct denali_controller *denali, u32 type, denali 1020 drivers/mtd/nand/raw/denali.c buf[i] = denali->host_read(denali, type | DENALI_BANK(denali)); denali 1023 drivers/mtd/nand/raw/denali.c static void denali_exec_in16(struct denali_controller *denali, u32 type, denali 1030 drivers/mtd/nand/raw/denali.c data = denali->host_read(denali, type | DENALI_BANK(denali)); denali 1037 drivers/mtd/nand/raw/denali.c static void denali_exec_in(struct denali_controller *denali, u32 type, denali 1041 drivers/mtd/nand/raw/denali.c denali_exec_in16(denali, type, buf, len); denali 1043 drivers/mtd/nand/raw/denali.c denali_exec_in8(denali, type, buf, len); denali 1046 drivers/mtd/nand/raw/denali.c static void denali_exec_out8(struct denali_controller *denali, u32 type, denali 1052 drivers/mtd/nand/raw/denali.c denali->host_write(denali, type | DENALI_BANK(denali), buf[i]); denali 1055 drivers/mtd/nand/raw/denali.c static void denali_exec_out16(struct denali_controller *denali, u32 type, denali 1061 drivers/mtd/nand/raw/denali.c denali->host_write(denali, type | DENALI_BANK(denali), denali 1065 drivers/mtd/nand/raw/denali.c static void denali_exec_out(struct denali_controller *denali, u32 type, denali 1069 drivers/mtd/nand/raw/denali.c denali_exec_out16(denali, type, buf, len); denali 1071 drivers/mtd/nand/raw/denali.c denali_exec_out8(denali, type, buf, len); denali 1074 drivers/mtd/nand/raw/denali.c static int denali_exec_waitrdy(struct denali_controller *denali) denali 1079 drivers/mtd/nand/raw/denali.c irq_stat = denali_wait_for_irq(denali, INTR__INT_ACT); denali 1082 drivers/mtd/nand/raw/denali.c denali_reset_irq(denali); denali 1090 drivers/mtd/nand/raw/denali.c struct denali_controller *denali = to_denali_controller(chip); denali 1094 drivers/mtd/nand/raw/denali.c denali_exec_out8(denali, DENALI_MAP11_CMD, denali 1098 drivers/mtd/nand/raw/denali.c denali_exec_out8(denali, DENALI_MAP11_ADDR, denali 1103 drivers/mtd/nand/raw/denali.c denali_exec_in(denali, DENALI_MAP11_DATA, denali 1110 drivers/mtd/nand/raw/denali.c denali_exec_out(denali, DENALI_MAP11_DATA, denali 1117 drivers/mtd/nand/raw/denali.c return denali_exec_waitrdy(denali); denali 1157 drivers/mtd/nand/raw/denali.c int denali_chip_init(struct denali_controller *denali, denali 1165 drivers/mtd/nand/raw/denali.c chip->controller = &denali->controller; denali 1171 drivers/mtd/nand/raw/denali.c if (bank >= denali->nbanks) { denali 1172 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "unsupported bank %d\n", bank); denali 1178 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, denali 1185 drivers/mtd/nand/raw/denali.c list_for_each_entry(dchip2, &denali->chips, node) { denali 1188 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, denali 1197 drivers/mtd/nand/raw/denali.c mtd->dev.parent = denali->dev; denali 1203 drivers/mtd/nand/raw/denali.c if (!mtd->name && list_empty(&denali->chips)) denali 1206 drivers/mtd/nand/raw/denali.c if (denali->dma_avail) { denali 1212 drivers/mtd/nand/raw/denali.c if (!denali->clk_rate || !denali->clk_x_rate) denali 1234 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "Failed to register MTD: %d\n", ret); denali 1238 drivers/mtd/nand/raw/denali.c list_add_tail(&dchip->node, &denali->chips); denali 1249 drivers/mtd/nand/raw/denali.c int denali_init(struct denali_controller *denali) denali 1251 drivers/mtd/nand/raw/denali.c u32 features = ioread32(denali->reg + FEATURES); denali 1254 drivers/mtd/nand/raw/denali.c nand_controller_init(&denali->controller); denali 1255 drivers/mtd/nand/raw/denali.c denali->controller.ops = &denali_controller_ops; denali 1256 drivers/mtd/nand/raw/denali.c init_completion(&denali->complete); denali 1257 drivers/mtd/nand/raw/denali.c spin_lock_init(&denali->irq_lock); denali 1258 drivers/mtd/nand/raw/denali.c INIT_LIST_HEAD(&denali->chips); denali 1259 drivers/mtd/nand/raw/denali.c denali->active_bank = DENALI_INVALID_BANK; denali 1265 drivers/mtd/nand/raw/denali.c if (!denali->revision) denali 1266 drivers/mtd/nand/raw/denali.c denali->revision = swab16(ioread32(denali->reg + REVISION)); denali 1268 drivers/mtd/nand/raw/denali.c denali->nbanks = 1 << FIELD_GET(FEATURES__N_BANKS, features); denali 1271 drivers/mtd/nand/raw/denali.c if (denali->revision < 0x0501) denali 1272 drivers/mtd/nand/raw/denali.c denali->nbanks <<= 1; denali 1275 drivers/mtd/nand/raw/denali.c denali->dma_avail = true; denali 1277 drivers/mtd/nand/raw/denali.c if (denali->dma_avail) { denali 1278 drivers/mtd/nand/raw/denali.c int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; denali 1280 drivers/mtd/nand/raw/denali.c ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); denali 1282 drivers/mtd/nand/raw/denali.c dev_info(denali->dev, denali 1284 drivers/mtd/nand/raw/denali.c denali->dma_avail = false; denali 1288 drivers/mtd/nand/raw/denali.c if (denali->dma_avail) { denali 1289 drivers/mtd/nand/raw/denali.c if (denali->caps & DENALI_CAP_DMA_64BIT) denali 1290 drivers/mtd/nand/raw/denali.c denali->setup_dma = denali_setup_dma64; denali 1292 drivers/mtd/nand/raw/denali.c denali->setup_dma = denali_setup_dma32; denali 1296 drivers/mtd/nand/raw/denali.c denali->host_read = denali_indexed_read; denali 1297 drivers/mtd/nand/raw/denali.c denali->host_write = denali_indexed_write; denali 1299 drivers/mtd/nand/raw/denali.c denali->host_read = denali_direct_read; denali 1300 drivers/mtd/nand/raw/denali.c denali->host_write = denali_direct_write; denali 1308 drivers/mtd/nand/raw/denali.c denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); denali 1309 drivers/mtd/nand/raw/denali.c if (!denali->oob_skip_bytes) { denali 1310 drivers/mtd/nand/raw/denali.c denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES; denali 1311 drivers/mtd/nand/raw/denali.c iowrite32(denali->oob_skip_bytes, denali 1312 drivers/mtd/nand/raw/denali.c denali->reg + SPARE_AREA_SKIP_BYTES); denali 1315 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + TRANSFER_SPARE_REG); denali 1316 drivers/mtd/nand/raw/denali.c iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED); denali 1317 drivers/mtd/nand/raw/denali.c iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); denali 1318 drivers/mtd/nand/raw/denali.c iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); denali 1319 drivers/mtd/nand/raw/denali.c iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); denali 1321 drivers/mtd/nand/raw/denali.c denali_clear_irq_all(denali); denali 1323 drivers/mtd/nand/raw/denali.c ret = devm_request_irq(denali->dev, denali->irq, denali_isr, denali 1324 drivers/mtd/nand/raw/denali.c IRQF_SHARED, DENALI_NAND_NAME, denali); denali 1326 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "Unable to request IRQ\n"); denali 1330 drivers/mtd/nand/raw/denali.c denali_enable_irq(denali); denali 1336 drivers/mtd/nand/raw/denali.c void denali_remove(struct denali_controller *denali) denali 1340 drivers/mtd/nand/raw/denali.c list_for_each_entry(dchip, &denali->chips, node) denali 1343 drivers/mtd/nand/raw/denali.c denali_disable_irq(denali); denali 382 drivers/mtd/nand/raw/denali.h u32 (*host_read)(struct denali_controller *denali, u32 addr); denali 383 drivers/mtd/nand/raw/denali.h void (*host_write)(struct denali_controller *denali, u32 addr, denali 385 drivers/mtd/nand/raw/denali.h void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr, denali 393 drivers/mtd/nand/raw/denali.h int denali_chip_init(struct denali_controller *denali, denali 395 drivers/mtd/nand/raw/denali.h int denali_init(struct denali_controller *denali); denali 396 drivers/mtd/nand/raw/denali.h void denali_remove(struct denali_controller *denali); denali 74 drivers/mtd/nand/raw/denali_dt.c static int denali_dt_chip_init(struct denali_controller *denali, denali 85 drivers/mtd/nand/raw/denali_dt.c dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), denali 102 drivers/mtd/nand/raw/denali_dt.c return denali_chip_init(denali, dchip); denali 106 drivers/mtd/nand/raw/denali_dt.c static int denali_dt_legacy_chip_init(struct denali_controller *denali) denali 111 drivers/mtd/nand/raw/denali_dt.c nsels = denali->nbanks; denali 113 drivers/mtd/nand/raw/denali_dt.c dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), denali 123 drivers/mtd/nand/raw/denali_dt.c nand_set_flash_node(&dchip->chip, denali->dev->of_node); denali 125 drivers/mtd/nand/raw/denali_dt.c return denali_chip_init(denali, dchip); denali 152 drivers/mtd/nand/raw/denali_dt.c struct denali_controller *denali; denali 159 drivers/mtd/nand/raw/denali_dt.c denali = &dt->controller; denali 163 drivers/mtd/nand/raw/denali_dt.c denali->revision = data->revision; denali 164 drivers/mtd/nand/raw/denali_dt.c denali->caps = data->caps; denali 165 drivers/mtd/nand/raw/denali_dt.c denali->ecc_caps = data->ecc_caps; denali 168 drivers/mtd/nand/raw/denali_dt.c denali->dev = dev; denali 169 drivers/mtd/nand/raw/denali_dt.c denali->irq = platform_get_irq(pdev, 0); denali 170 drivers/mtd/nand/raw/denali_dt.c if (denali->irq < 0) { denali 172 drivers/mtd/nand/raw/denali_dt.c return denali->irq; denali 176 drivers/mtd/nand/raw/denali_dt.c denali->reg = devm_ioremap_resource(dev, res); denali 177 drivers/mtd/nand/raw/denali_dt.c if (IS_ERR(denali->reg)) denali 178 drivers/mtd/nand/raw/denali_dt.c return PTR_ERR(denali->reg); denali 181 drivers/mtd/nand/raw/denali_dt.c denali->host = devm_ioremap_resource(dev, res); denali 182 drivers/mtd/nand/raw/denali_dt.c if (IS_ERR(denali->host)) denali 183 drivers/mtd/nand/raw/denali_dt.c return PTR_ERR(denali->host); denali 209 drivers/mtd/nand/raw/denali_dt.c denali->clk_rate = clk_get_rate(dt->clk); denali 210 drivers/mtd/nand/raw/denali_dt.c denali->clk_x_rate = clk_get_rate(dt->clk_x); denali 212 drivers/mtd/nand/raw/denali_dt.c ret = denali_init(denali); denali 217 drivers/mtd/nand/raw/denali_dt.c ret = denali_dt_legacy_chip_init(denali); denali 222 drivers/mtd/nand/raw/denali_dt.c ret = denali_dt_chip_init(denali, np); denali 235 drivers/mtd/nand/raw/denali_dt.c denali_remove(denali); denali 34 drivers/mtd/nand/raw/denali_pci.c struct denali_controller *denali; denali 38 drivers/mtd/nand/raw/denali_pci.c denali = devm_kzalloc(&dev->dev, sizeof(*denali), GFP_KERNEL); denali 39 drivers/mtd/nand/raw/denali_pci.c if (!denali) denali 65 drivers/mtd/nand/raw/denali_pci.c denali->dev = &dev->dev; denali 66 drivers/mtd/nand/raw/denali_pci.c denali->irq = dev->irq; denali 67 drivers/mtd/nand/raw/denali_pci.c denali->ecc_caps = &denali_pci_ecc_caps; denali 68 drivers/mtd/nand/raw/denali_pci.c denali->clk_rate = 50000000; /* 50 MHz */ denali 69 drivers/mtd/nand/raw/denali_pci.c denali->clk_x_rate = 200000000; /* 200 MHz */ denali 77 drivers/mtd/nand/raw/denali_pci.c denali->reg = ioremap_nocache(csr_base, csr_len); denali 78 drivers/mtd/nand/raw/denali_pci.c if (!denali->reg) { denali 83 drivers/mtd/nand/raw/denali_pci.c denali->host = ioremap_nocache(mem_base, mem_len); denali 84 drivers/mtd/nand/raw/denali_pci.c if (!denali->host) { denali 90 drivers/mtd/nand/raw/denali_pci.c ret = denali_init(denali); denali 94 drivers/mtd/nand/raw/denali_pci.c nsels = denali->nbanks; denali 96 drivers/mtd/nand/raw/denali_pci.c dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), denali 110 drivers/mtd/nand/raw/denali_pci.c ret = denali_chip_init(denali, dchip); denali 114 drivers/mtd/nand/raw/denali_pci.c pci_set_drvdata(dev, denali); denali 119 drivers/mtd/nand/raw/denali_pci.c denali_remove(denali); denali 121 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->host); denali 123 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->reg); denali 129 drivers/mtd/nand/raw/denali_pci.c struct denali_controller *denali = pci_get_drvdata(dev); denali 131 drivers/mtd/nand/raw/denali_pci.c denali_remove(denali); denali 132 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->reg); denali 133 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->host); denali 1204 drivers/scsi/aacraid/aacraid.h } denali; denali 658 drivers/scsi/aacraid/src.c dev->base)->u.denali.IndexRegs;