DSCC_PPS_CONFIG3  159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
DSCC_PPS_CONFIG3  578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_2(DSCC_PPS_CONFIG3, 0,
DSCC_PPS_CONFIG3   45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG3, DSCC, id),\
DSCC_PPS_CONFIG3  470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	uint32_t DSCC_PPS_CONFIG3;