DSCC0_DSCC_PPS_CONFIG11  165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
DSCC0_DSCC_PPS_CONFIG11  166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
DSCC0_DSCC_PPS_CONFIG11  167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
DSCC0_DSCC_PPS_CONFIG11  168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
DSCC0_DSCC_PPS_CONFIG11  169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \