DSCC0_DSCC_PPS_CONFIG1  137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
DSCC0_DSCC_PPS_CONFIG1  144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \