DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
DSCC0_DSCC_INTERRUPT_CONTROL_STATUS  131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \