deemph_reg_value 3797 drivers/gpu/drm/i915/display/intel_dp.c u32 deemph_reg_value, margin_reg_value; deemph_reg_value 3805 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 128; deemph_reg_value 3809 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 128; deemph_reg_value 3813 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 128; deemph_reg_value 3817 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 128; deemph_reg_value 3828 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 85; deemph_reg_value 3832 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 85; deemph_reg_value 3836 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 85; deemph_reg_value 3846 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 64; deemph_reg_value 3850 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 64; deemph_reg_value 3860 drivers/gpu/drm/i915/display/intel_dp.c deemph_reg_value = 43; deemph_reg_value 3871 drivers/gpu/drm/i915/display/intel_dp.c chv_set_phy_signal_level(encoder, deemph_reg_value, deemph_reg_value 641 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 deemph_reg_value, u32 margin_reg_value, deemph_reg_value 685 drivers/gpu/drm/i915/display/intel_dpio_phy.c val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; deemph_reg_value 35 drivers/gpu/drm/i915/display/intel_dpio_phy.h u32 deemph_reg_value, u32 margin_reg_value,