ddrphycfg_parents  160 drivers/clk/mediatek/clk-mt2701.c static const char * const ddrphycfg_parents[] = {
ddrphycfg_parents  493 drivers/clk/mediatek/clk-mt2701.c 		ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
ddrphycfg_parents  104 drivers/clk/mediatek/clk-mt6797.c static const char * const ddrphycfg_parents[] = {
ddrphycfg_parents  330 drivers/clk/mediatek/clk-mt6797.c 	MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
ddrphycfg_parents  130 drivers/clk/mediatek/clk-mt7622.c static const char * const ddrphycfg_parents[] = {
ddrphycfg_parents  519 drivers/clk/mediatek/clk-mt7622.c 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
ddrphycfg_parents  561 drivers/clk/mediatek/clk-mt7622.c 	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
ddrphycfg_parents  106 drivers/clk/mediatek/clk-mt7629.c static const char * const ddrphycfg_parents[] = {
ddrphycfg_parents  491 drivers/clk/mediatek/clk-mt7629.c 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
ddrphycfg_parents  278 drivers/clk/mediatek/clk-mt8135.c static const char * const ddrphycfg_parents[] __initconst = {
ddrphycfg_parents  381 drivers/clk/mediatek/clk-mt8135.c 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
ddrphycfg_parents  147 drivers/clk/mediatek/clk-mt8173.c static const char * const ddrphycfg_parents[] __initconst = {
ddrphycfg_parents  544 drivers/clk/mediatek/clk-mt8173.c 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),