ddrclk             32 drivers/clk/rockchip/clk-ddr.c 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
ddrclk             36 drivers/clk/rockchip/clk-ddr.c 	spin_lock_irqsave(ddrclk->lock, flags);
ddrclk             40 drivers/clk/rockchip/clk-ddr.c 	spin_unlock_irqrestore(ddrclk->lock, flags);
ddrclk             73 drivers/clk/rockchip/clk-ddr.c 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
ddrclk             76 drivers/clk/rockchip/clk-ddr.c 	val = readl(ddrclk->reg_base +
ddrclk             77 drivers/clk/rockchip/clk-ddr.c 			ddrclk->mux_offset) >> ddrclk->mux_shift;
ddrclk             78 drivers/clk/rockchip/clk-ddr.c 	val &= GENMASK(ddrclk->mux_width - 1, 0);
ddrclk             98 drivers/clk/rockchip/clk-ddr.c 	struct rockchip_ddrclk *ddrclk;
ddrclk            102 drivers/clk/rockchip/clk-ddr.c 	ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
ddrclk            103 drivers/clk/rockchip/clk-ddr.c 	if (!ddrclk)
ddrclk            119 drivers/clk/rockchip/clk-ddr.c 		kfree(ddrclk);
ddrclk            123 drivers/clk/rockchip/clk-ddr.c 	ddrclk->reg_base = reg_base;
ddrclk            124 drivers/clk/rockchip/clk-ddr.c 	ddrclk->lock = lock;
ddrclk            125 drivers/clk/rockchip/clk-ddr.c 	ddrclk->hw.init = &init;
ddrclk            126 drivers/clk/rockchip/clk-ddr.c 	ddrclk->mux_offset = mux_offset;
ddrclk            127 drivers/clk/rockchip/clk-ddr.c 	ddrclk->mux_shift = mux_shift;
ddrclk            128 drivers/clk/rockchip/clk-ddr.c 	ddrclk->mux_width = mux_width;
ddrclk            129 drivers/clk/rockchip/clk-ddr.c 	ddrclk->div_shift = div_shift;
ddrclk            130 drivers/clk/rockchip/clk-ddr.c 	ddrclk->div_width = div_width;
ddrclk            131 drivers/clk/rockchip/clk-ddr.c 	ddrclk->ddr_flag = ddr_flag;
ddrclk            133 drivers/clk/rockchip/clk-ddr.c 	clk = clk_register(NULL, &ddrclk->hw);
ddrclk            135 drivers/clk/rockchip/clk-ddr.c 		kfree(ddrclk);