ddrc_pmu           64 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu,
ddrc_pmu           70 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
ddrc_pmu           71 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
ddrc_pmu           75 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
ddrc_pmu           78 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu,
ddrc_pmu           83 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
ddrc_pmu           84 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
ddrc_pmu           89 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	       ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
ddrc_pmu          101 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu)
ddrc_pmu          106 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
ddrc_pmu          108 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
ddrc_pmu          111 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu)
ddrc_pmu          116 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
ddrc_pmu          118 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
ddrc_pmu          121 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
ddrc_pmu          127 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
ddrc_pmu          129 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
ddrc_pmu          132 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
ddrc_pmu          138 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
ddrc_pmu          140 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
ddrc_pmu          145 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
ddrc_pmu          146 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
ddrc_pmu          159 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
ddrc_pmu          165 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_INT_MASK);
ddrc_pmu          167 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_INT_MASK);
ddrc_pmu          170 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
ddrc_pmu          176 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	val = readl(ddrc_pmu->base + DDRC_INT_MASK);
ddrc_pmu          178 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	writel(val, ddrc_pmu->base + DDRC_INT_MASK);
ddrc_pmu          183 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	struct hisi_pmu *ddrc_pmu = dev_id;
ddrc_pmu          189 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS);
ddrc_pmu          199 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		writel((1 << idx), ddrc_pmu->base + DDRC_INT_CLEAR);
ddrc_pmu          202 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		event = ddrc_pmu->pmu_events.hw_events[idx];
ddrc_pmu          213 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c static int hisi_ddrc_pmu_init_irq(struct hisi_pmu *ddrc_pmu,
ddrc_pmu          225 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 			       dev_name(&pdev->dev), ddrc_pmu);
ddrc_pmu          232 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->irq = irq;
ddrc_pmu          244 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				   struct hisi_pmu *ddrc_pmu)
ddrc_pmu          253 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				     &ddrc_pmu->index_id)) {
ddrc_pmu          259 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				     &ddrc_pmu->sccl_id)) {
ddrc_pmu          264 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->ccl_id = -1;
ddrc_pmu          267 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res);
ddrc_pmu          268 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	if (IS_ERR(ddrc_pmu->base)) {
ddrc_pmu          270 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		return PTR_ERR(ddrc_pmu->base);
ddrc_pmu          335 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				   struct hisi_pmu *ddrc_pmu)
ddrc_pmu          339 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ret = hisi_ddrc_pmu_init_data(pdev, ddrc_pmu);
ddrc_pmu          343 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ret = hisi_ddrc_pmu_init_irq(ddrc_pmu, pdev);
ddrc_pmu          347 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
ddrc_pmu          348 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->counter_bits = 32;
ddrc_pmu          349 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
ddrc_pmu          350 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->dev = &pdev->dev;
ddrc_pmu          351 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->on_cpu = -1;
ddrc_pmu          352 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->check_event = 7;
ddrc_pmu          359 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	struct hisi_pmu *ddrc_pmu;
ddrc_pmu          363 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddrc_pmu), GFP_KERNEL);
ddrc_pmu          364 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	if (!ddrc_pmu)
ddrc_pmu          367 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	platform_set_drvdata(pdev, ddrc_pmu);
ddrc_pmu          369 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ret = hisi_ddrc_pmu_dev_probe(pdev, ddrc_pmu);
ddrc_pmu          374 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				       &ddrc_pmu->node);
ddrc_pmu          381 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 			      ddrc_pmu->sccl_id, ddrc_pmu->index_id);
ddrc_pmu          382 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ddrc_pmu->pmu = (struct pmu) {
ddrc_pmu          397 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
ddrc_pmu          399 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 		dev_err(ddrc_pmu->dev, "DDRC PMU register failed!\n");
ddrc_pmu          401 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 					    &ddrc_pmu->node);
ddrc_pmu          409 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
ddrc_pmu          411 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 	perf_pmu_unregister(&ddrc_pmu->pmu);
ddrc_pmu          413 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c 				    &ddrc_pmu->node);