ddr_div           126 arch/mips/ath79/clock.c 	u32 mult, div, ddr_div, ahb_div;
ddr_div           136 arch/mips/ath79/clock.c 	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ddr_div           140 arch/mips/ath79/clock.c 	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
ddr_div           153 arch/mips/ath79/clock.c 	u32 ddr_div;
ddr_div           172 arch/mips/ath79/clock.c 		ddr_div = 1;
ddr_div           197 arch/mips/ath79/clock.c 		ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
ddr_div           207 arch/mips/ath79/clock.c 			 ref_div * out_div * ddr_div);