ddi_select        213 drivers/gpu/drm/gma500/cdv_intel_display.c 		       struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
ddi_select        256 drivers/gpu/drm/gma500/cdv_intel_display.c 	if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
ddi_select        333 drivers/gpu/drm/gma500/cdv_intel_display.c 	if (ddi_select) {
ddi_select        334 drivers/gpu/drm/gma500/cdv_intel_display.c 		if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
ddi_select        588 drivers/gpu/drm/gma500/cdv_intel_display.c 	u32 ddi_select = 0;
ddi_select        599 drivers/gpu/drm/gma500/cdv_intel_display.c 		ddi_select = gma_encoder->ddi_select;
ddi_select        729 drivers/gpu/drm/gma500/cdv_intel_display.c 	cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
ddi_select       2050 drivers/gpu/drm/gma500/cdv_intel_dp.c 			gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
ddi_select       2054 drivers/gpu/drm/gma500/cdv_intel_dp.c 			gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
ddi_select        337 drivers/gpu/drm/gma500/cdv_intel_hdmi.c 		gma_encoder->ddi_select = DDI0_SELECT;
ddi_select        341 drivers/gpu/drm/gma500/cdv_intel_hdmi.c 		gma_encoder->ddi_select = DDI1_SELECT;
ddi_select        116 drivers/gpu/drm/gma500/psb_intel_drv.h 	u32 ddi_select;	/* Channel info */
ddi_select       2017 drivers/gpu/drm/i915/display/intel_ddi.c 		unsigned int port_mask, ddi_select;
ddi_select       2027 drivers/gpu/drm/i915/display/intel_ddi.c 			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
ddi_select       2030 drivers/gpu/drm/i915/display/intel_ddi.c 			ddi_select = TRANS_DDI_SELECT_PORT(port);
ddi_select       2037 drivers/gpu/drm/i915/display/intel_ddi.c 		if ((tmp & port_mask) != ddi_select)