ddi_pll_sel      1071 drivers/gpu/drm/i915/display/intel_ddi.c 	u32 temp, i, rx_ctl_val, ddi_pll_sel;
ddi_pll_sel      1102 drivers/gpu/drm/i915/display/intel_ddi.c 	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
ddi_pll_sel      1103 drivers/gpu/drm/i915/display/intel_ddi.c 	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
ddi_pll_sel      1104 drivers/gpu/drm/i915/display/intel_ddi.c 	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
ddi_pll_sel      10169 drivers/gpu/drm/i915/display/intel_display.c 	u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
ddi_pll_sel      10171 drivers/gpu/drm/i915/display/intel_display.c 	switch (ddi_pll_sel) {
ddi_pll_sel      10191 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(ddi_pll_sel);