ddc_handle        124 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        136 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
ddc_handle        140 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        142 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        145 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        157 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SDA, true);
ddc_handle        161 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        163 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        168 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	ack = !read_bit_from_ddc(ddc_handle, SDA);
ddc_handle        172 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        181 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        195 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        197 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        200 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (read_bit_from_ddc(ddc_handle, SDA))
ddc_handle        203 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        220 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SDA, !more);
ddc_handle        224 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        226 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        229 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        233 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SDA, true);
ddc_handle        241 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        250 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        254 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SDA, false);
ddc_handle        258 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        260 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        263 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SDA, true);
ddc_handle        268 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (read_bit_from_ddc(ddc_handle, SDA))
ddc_handle        278 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        286 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, address))
ddc_handle        290 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, data[i]))
ddc_handle        300 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        308 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, address))
ddc_handle        312 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!read_byte_sw(ctx, ddc_handle, clock_delay_div_4, data + i,
ddc_handle        325 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle,
ddc_handle        334 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        339 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SDA, true);
ddc_handle        341 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!read_bit_from_ddc(ddc_handle, SDA)) {
ddc_handle        348 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, true);
ddc_handle        350 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
ddc_handle        353 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SDA, false);
ddc_handle        357 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		write_bit_to_ddc(ddc_handle, SCL, false);
ddc_handle        399 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc_handle)
ddc_handle        407 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 				dce_i2c_sw, ddc_handle);