ddc_base           49 drivers/video/fbdev/i810/i810-i2c.c 		i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
ddc_base           51 drivers/video/fbdev/i810/i810-i2c.c 		i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
ddc_base           52 drivers/video/fbdev/i810/i810-i2c.c 	i810_readl(mmio, chan->ddc_base);	/* flush posted write */
ddc_base           62 drivers/video/fbdev/i810/i810-i2c.c 		i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
ddc_base           64 drivers/video/fbdev/i810/i810-i2c.c 		i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
ddc_base           65 drivers/video/fbdev/i810/i810-i2c.c 	i810_readl(mmio, chan->ddc_base);	/* flush posted write */
ddc_base           74 drivers/video/fbdev/i810/i810-i2c.c 	i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK);
ddc_base           75 drivers/video/fbdev/i810/i810-i2c.c 	i810_writel(mmio, chan->ddc_base, 0);
ddc_base           76 drivers/video/fbdev/i810/i810-i2c.c 	return ((i810_readl(mmio, chan->ddc_base) & SCL_VAL_IN) != 0);
ddc_base           85 drivers/video/fbdev/i810/i810-i2c.c 	i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK);
ddc_base           86 drivers/video/fbdev/i810/i810-i2c.c 	i810_writel(mmio, chan->ddc_base, 0);
ddc_base           87 drivers/video/fbdev/i810/i810-i2c.c 	return ((i810_readl(mmio, chan->ddc_base) & SDA_VAL_IN) != 0);
ddc_base          132 drivers/video/fbdev/i810/i810-i2c.c 	par->chan[0].ddc_base = GPIOA;
ddc_base          134 drivers/video/fbdev/i810/i810-i2c.c 	par->chan[1].ddc_base = GPIOB;
ddc_base          136 drivers/video/fbdev/i810/i810-i2c.c 	par->chan[2].ddc_base = GPIOC;
ddc_base          250 drivers/video/fbdev/i810/i810.h 	unsigned long ddc_base;
ddc_base           34 drivers/video/fbdev/nvidia/nv_i2c.c 	val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
ddc_base           41 drivers/video/fbdev/nvidia/nv_i2c.c 	NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
ddc_base           50 drivers/video/fbdev/nvidia/nv_i2c.c 	val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
ddc_base           57 drivers/video/fbdev/nvidia/nv_i2c.c 	NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
ddc_base           66 drivers/video/fbdev/nvidia/nv_i2c.c 	if (NVReadCrtc(par, chan->ddc_base) & 0x04)
ddc_base           78 drivers/video/fbdev/nvidia/nv_i2c.c 	if (NVReadCrtc(par, chan->ddc_base) & 0x08)
ddc_base          128 drivers/video/fbdev/nvidia/nv_i2c.c 	par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e;
ddc_base          132 drivers/video/fbdev/nvidia/nv_i2c.c 	par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36;
ddc_base          136 drivers/video/fbdev/nvidia/nv_i2c.c 	par->chan[2].ddc_base = 0x50;
ddc_base           43 drivers/video/fbdev/nvidia/nv_type.h 	unsigned long ddc_base;
ddc_base           33 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
ddc_base           41 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
ddc_base           51 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
ddc_base           59 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
ddc_base           69 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
ddc_base           82 drivers/video/fbdev/riva/rivafb-i2c.c 	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
ddc_base          132 drivers/video/fbdev/riva/rivafb-i2c.c 	par->chan[0].ddc_base = 0x36;
ddc_base          133 drivers/video/fbdev/riva/rivafb-i2c.c 	par->chan[1].ddc_base = 0x3e;
ddc_base          134 drivers/video/fbdev/riva/rivafb-i2c.c 	par->chan[2].ddc_base = 0x50;
ddc_base           39 drivers/video/fbdev/riva/rivafb.h 	unsigned long   ddc_base;