dctlreg          1813 drivers/vme/bridges/vme_tsi148.c 	u32 val, dctlreg = 0;
dctlreg          1853 drivers/vme/bridges/vme_tsi148.c 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
dctlreg          1857 drivers/vme/bridges/vme_tsi148.c 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
dctlreg          1864 drivers/vme/bridges/vme_tsi148.c 		iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +