dct_sel_lo       1646 drivers/edac/amd64_edac.c 	if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
dct_sel_lo       1648 drivers/edac/amd64_edac.c 			 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
dct_sel_lo       1708 drivers/edac/amd64_edac.c 	u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
dct_sel_lo        197 drivers/edac/amd64_edac.h #define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
dct_sel_lo        198 drivers/edac/amd64_edac.h #define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))
dct_sel_lo        200 drivers/edac/amd64_edac.h #define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
dct_sel_lo        202 drivers/edac/amd64_edac.h #define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
dct_sel_lo        203 drivers/edac/amd64_edac.h #define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))
dct_sel_lo        372 drivers/edac/amd64_edac.h 	u32 dct_sel_lo;		/* DRAM Controller Select Low */
dct_sel_lo        442 drivers/edac/amd64_edac.h 			((pvt->dct_sel_lo >> 6) & 0x3);
dct_sel_lo        444 drivers/edac/amd64_edac.h 	return	((pvt)->dct_sel_lo >> 6) & 0x3;
dct_sel_lo        540 drivers/edac/amd64_edac.h 	return (pvt)->dct_sel_lo & 0xFFFFF800;