dct_cont_base_reg 1991 drivers/edac/amd64_edac.c u32 dct_cont_base_reg, dct_cont_limit_reg, tmp; dct_cont_base_reg 1999 drivers/edac/amd64_edac.c amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); dct_cont_base_reg 2002 drivers/edac/amd64_edac.c dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0)); dct_cont_base_reg 2003 drivers/edac/amd64_edac.c dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7); dct_cont_base_reg 2024 drivers/edac/amd64_edac.c if (!(dct_cont_base_reg & BIT(0)) && dct_cont_base_reg 2045 drivers/edac/amd64_edac.c leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));