dcrtc 19 drivers/gpu/drm/armada/armada_510.c static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) dcrtc 29 drivers/gpu/drm/armada/armada_510.c dcrtc->variant_data = v; dcrtc 69 drivers/gpu/drm/armada/armada_510.c dcrtc->base + LCD_CFG_RDREG4F); dcrtc 73 drivers/gpu/drm/armada/armada_510.c dcrtc->base + LCD_SPU_ADV_REG); dcrtc 100 drivers/gpu/drm/armada/armada_510.c static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, dcrtc 103 drivers/gpu/drm/armada/armada_510.c struct armada510_variant_data *v = dcrtc->variant_data; dcrtc 108 drivers/gpu/drm/armada/armada_510.c idx = armada_crtc_select_clock(dcrtc, &res, &armada510_clocking, dcrtc 125 drivers/gpu/drm/armada/armada_510.c swap(dcrtc->clk, res.clk); dcrtc 133 drivers/gpu/drm/armada/armada_510.c static void armada510_crtc_disable(struct armada_crtc *dcrtc) dcrtc 135 drivers/gpu/drm/armada/armada_510.c if (dcrtc->clk) { dcrtc 136 drivers/gpu/drm/armada/armada_510.c clk_disable_unprepare(dcrtc->clk); dcrtc 137 drivers/gpu/drm/armada/armada_510.c dcrtc->clk = NULL; dcrtc 141 drivers/gpu/drm/armada/armada_510.c static void armada510_crtc_enable(struct armada_crtc *dcrtc, dcrtc 144 drivers/gpu/drm/armada/armada_510.c struct armada510_variant_data *v = dcrtc->variant_data; dcrtc 146 drivers/gpu/drm/armada/armada_510.c if (!dcrtc->clk && v->sel_clk) { dcrtc 148 drivers/gpu/drm/armada/armada_510.c dcrtc->clk = v->sel_clk; dcrtc 82 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) dcrtc 85 drivers/gpu/drm/armada/armada_crtc.c void __iomem *reg = dcrtc->base + regs->offset; dcrtc 96 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_update(struct armada_crtc *dcrtc, bool enable) dcrtc 100 drivers/gpu/drm/armada/armada_crtc.c dumb_ctrl = dcrtc->cfg_dumb_ctrl; dcrtc 118 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_DUMB_CTRL); dcrtc 123 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 130 drivers/gpu/drm/armada/armada_crtc.c dcrtc->event = event; dcrtc 175 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 187 drivers/gpu/drm/armada/armada_crtc.c if (!dcrtc->variant->has_spu_adv_reg && dcrtc 202 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 220 drivers/gpu/drm/armada/armada_crtc.c ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); dcrtc 228 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) dcrtc 230 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->irq_ena & mask) { dcrtc 231 drivers/gpu/drm/armada/armada_crtc.c dcrtc->irq_ena &= ~mask; dcrtc 232 drivers/gpu/drm/armada/armada_crtc.c writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); dcrtc 236 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) dcrtc 238 drivers/gpu/drm/armada/armada_crtc.c if ((dcrtc->irq_ena & mask) != mask) { dcrtc 239 drivers/gpu/drm/armada/armada_crtc.c dcrtc->irq_ena |= mask; dcrtc 240 drivers/gpu/drm/armada/armada_crtc.c writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); dcrtc 241 drivers/gpu/drm/armada/armada_crtc.c if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) dcrtc 242 drivers/gpu/drm/armada/armada_crtc.c writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); dcrtc 246 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) dcrtc 249 drivers/gpu/drm/armada/armada_crtc.c void __iomem *base = dcrtc->base; dcrtc 252 drivers/gpu/drm/armada/armada_crtc.c DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); dcrtc 254 drivers/gpu/drm/armada/armada_crtc.c DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); dcrtc 257 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_handle_vblank(&dcrtc->crtc); dcrtc 259 drivers/gpu/drm/armada/armada_crtc.c spin_lock(&dcrtc->irq_lock); dcrtc 260 drivers/gpu/drm/armada/armada_crtc.c if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { dcrtc 264 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); dcrtc 265 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->v[i].spu_v_h_total, dcrtc 270 drivers/gpu/drm/armada/armada_crtc.c val |= dcrtc->v[i].spu_adv_reg; dcrtc 274 drivers/gpu/drm/armada/armada_crtc.c if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { dcrtc 275 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->update_pending) { dcrtc 276 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); dcrtc 277 drivers/gpu/drm/armada/armada_crtc.c dcrtc->update_pending = false; dcrtc 279 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_update) { dcrtc 280 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->cursor_hw_pos, dcrtc 282 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->cursor_hw_sz, dcrtc 288 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_update = false; dcrtc 290 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); dcrtc 292 drivers/gpu/drm/armada/armada_crtc.c spin_unlock(&dcrtc->irq_lock); dcrtc 294 drivers/gpu/drm/armada/armada_crtc.c if (stat & VSYNC_IRQ && !dcrtc->update_pending) { dcrtc 295 drivers/gpu/drm/armada/armada_crtc.c event = xchg(&dcrtc->event, NULL); dcrtc 297 drivers/gpu/drm/armada/armada_crtc.c spin_lock(&dcrtc->crtc.dev->event_lock); dcrtc 298 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_send_vblank_event(&dcrtc->crtc, event); dcrtc 299 drivers/gpu/drm/armada/armada_crtc.c spin_unlock(&dcrtc->crtc.dev->event_lock); dcrtc 300 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_vblank_put(&dcrtc->crtc); dcrtc 307 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = arg; dcrtc 308 drivers/gpu/drm/armada/armada_crtc.c u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); dcrtc 315 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); dcrtc 317 drivers/gpu/drm/armada/armada_crtc.c trace_armada_drm_irq(&dcrtc->crtc, stat); dcrtc 320 drivers/gpu/drm/armada/armada_crtc.c v = stat & dcrtc->irq_ena; dcrtc 323 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_irq(dcrtc, stat); dcrtc 333 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 351 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant->compute_clock(dcrtc, adj, &sclk); dcrtc 355 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irqsave(&dcrtc->irq_lock, flags); dcrtc 357 drivers/gpu/drm/armada/armada_crtc.c dcrtc->interlaced = interlaced; dcrtc 359 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | dcrtc 361 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[1].spu_v_porch = tm << 16 | bm; dcrtc 363 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; dcrtc 368 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; dcrtc 369 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + dcrtc 371 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; dcrtc 373 drivers/gpu/drm/armada/armada_crtc.c dcrtc->v[0] = dcrtc->v[1]; dcrtc 380 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); dcrtc 381 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, dcrtc 384 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->variant->has_spu_adv_reg) dcrtc 385 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, dcrtc 411 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update_regs(dcrtc, regs); dcrtc 412 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irqrestore(&dcrtc->irq_lock, flags); dcrtc 432 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 439 drivers/gpu/drm/armada/armada_crtc.c dcrtc->regs_idx = 0; dcrtc 440 drivers/gpu/drm/armada/armada_crtc.c dcrtc->regs = dcrtc->atomic_regs; dcrtc 446 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 450 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); dcrtc 457 drivers/gpu/drm/armada/armada_crtc.c dcrtc->update_pending = true; dcrtc 459 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 460 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); dcrtc 461 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 463 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 464 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); dcrtc 465 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 472 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 481 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update(dcrtc, false); dcrtc 488 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->variant->disable) dcrtc 489 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant->disable(dcrtc); dcrtc 508 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 518 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->variant->enable) dcrtc 519 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant->enable(dcrtc, &crtc->state->adjusted_mode); dcrtc 521 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_update(dcrtc, true); dcrtc 592 drivers/gpu/drm/armada/armada_crtc.c static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) dcrtc 594 drivers/gpu/drm/armada/armada_crtc.c uint32_t xoff, xscr, w = dcrtc->cursor_w, s; dcrtc 595 drivers/gpu/drm/armada/armada_crtc.c uint32_t yoff, yscr, h = dcrtc->cursor_h; dcrtc 602 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_x < 0) { dcrtc 603 drivers/gpu/drm/armada/armada_crtc.c xoff = -dcrtc->cursor_x; dcrtc 606 drivers/gpu/drm/armada/armada_crtc.c } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { dcrtc 608 drivers/gpu/drm/armada/armada_crtc.c xscr = dcrtc->cursor_x; dcrtc 609 drivers/gpu/drm/armada/armada_crtc.c w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); dcrtc 612 drivers/gpu/drm/armada/armada_crtc.c xscr = dcrtc->cursor_x; dcrtc 615 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_y < 0) { dcrtc 616 drivers/gpu/drm/armada/armada_crtc.c yoff = -dcrtc->cursor_y; dcrtc 619 drivers/gpu/drm/armada/armada_crtc.c } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { dcrtc 621 drivers/gpu/drm/armada/armada_crtc.c yscr = dcrtc->cursor_y; dcrtc 622 drivers/gpu/drm/armada/armada_crtc.c h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); dcrtc 625 drivers/gpu/drm/armada/armada_crtc.c yscr = dcrtc->cursor_y; dcrtc 629 drivers/gpu/drm/armada/armada_crtc.c s = dcrtc->cursor_w; dcrtc 630 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->interlaced) { dcrtc 636 drivers/gpu/drm/armada/armada_crtc.c if (!dcrtc->cursor_obj || !h || !w) { dcrtc 637 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 638 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_update = false; dcrtc 639 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); dcrtc 640 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 644 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 645 drivers/gpu/drm/armada/armada_crtc.c para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); dcrtc 647 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_SRAM_PARA1); dcrtc 648 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 655 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_cursor_tran(dcrtc->base); dcrtc 659 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_hw_sz != (h << 16 | w)) { dcrtc 660 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 661 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_update = false; dcrtc 662 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); dcrtc 663 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 667 drivers/gpu/drm/armada/armada_crtc.c struct armada_gem_object *obj = dcrtc->cursor_obj; dcrtc 672 drivers/gpu/drm/armada/armada_crtc.c armada_load_cursor_argb(dcrtc->base, pix, s, w, h); dcrtc 676 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irq(&dcrtc->irq_lock); dcrtc 677 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_hw_pos = yscr << 16 | xscr; dcrtc 678 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_hw_sz = h << 16 | w; dcrtc 679 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_update = true; dcrtc 680 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); dcrtc 681 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irq(&dcrtc->irq_lock); dcrtc 694 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 699 drivers/gpu/drm/armada/armada_crtc.c if (!dcrtc->variant->has_spu_adv_reg) dcrtc 724 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_obj) { dcrtc 725 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_obj->update = NULL; dcrtc 726 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_obj->update_data = NULL; dcrtc 727 drivers/gpu/drm/armada/armada_crtc.c drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj); dcrtc 729 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_obj = obj; dcrtc 730 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_w = w; dcrtc 731 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_h = h; dcrtc 732 drivers/gpu/drm/armada/armada_crtc.c ret = armada_drm_crtc_cursor_update(dcrtc, true); dcrtc 734 drivers/gpu/drm/armada/armada_crtc.c obj->update_data = dcrtc; dcrtc 743 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 747 drivers/gpu/drm/armada/armada_crtc.c if (!dcrtc->variant->has_spu_adv_reg) dcrtc 750 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_x = x; dcrtc 751 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cursor_y = y; dcrtc 752 drivers/gpu/drm/armada/armada_crtc.c ret = armada_drm_crtc_cursor_update(dcrtc, false); dcrtc 759 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 762 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->cursor_obj) dcrtc 763 drivers/gpu/drm/armada/armada_crtc.c drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj); dcrtc 765 drivers/gpu/drm/armada/armada_crtc.c priv->dcrtc[dcrtc->num] = NULL; dcrtc 766 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_cleanup(&dcrtc->crtc); dcrtc 768 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->variant->disable) dcrtc 769 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant->disable(dcrtc); dcrtc 771 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); dcrtc 773 drivers/gpu/drm/armada/armada_crtc.c of_node_put(dcrtc->crtc.port); dcrtc 775 drivers/gpu/drm/armada/armada_crtc.c kfree(dcrtc); dcrtc 789 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 792 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irqsave(&dcrtc->irq_lock, flags); dcrtc 793 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA); dcrtc 794 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irqrestore(&dcrtc->irq_lock, flags); dcrtc 800 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); dcrtc 803 drivers/gpu/drm/armada/armada_crtc.c spin_lock_irqsave(&dcrtc->irq_lock, flags); dcrtc 804 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA); dcrtc 805 drivers/gpu/drm/armada/armada_crtc.c spin_unlock_irqrestore(&dcrtc->irq_lock, flags); dcrtc 823 drivers/gpu/drm/armada/armada_crtc.c int armada_crtc_select_clock(struct armada_crtc *dcrtc, dcrtc 839 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz); dcrtc 870 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, dcrtc 890 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, dcrtc 905 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc; dcrtc 914 drivers/gpu/drm/armada/armada_crtc.c dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); dcrtc 915 drivers/gpu/drm/armada/armada_crtc.c if (!dcrtc) { dcrtc 921 drivers/gpu/drm/armada/armada_crtc.c dev_set_drvdata(dev, dcrtc); dcrtc 923 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant = variant; dcrtc 924 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base = base; dcrtc 925 drivers/gpu/drm/armada/armada_crtc.c dcrtc->num = drm->mode_config.num_crtc; dcrtc 926 drivers/gpu/drm/armada/armada_crtc.c dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; dcrtc 927 drivers/gpu/drm/armada/armada_crtc.c dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; dcrtc 928 drivers/gpu/drm/armada/armada_crtc.c spin_lock_init(&dcrtc->irq_lock); dcrtc 929 drivers/gpu/drm/armada/armada_crtc.c dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; dcrtc 932 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); dcrtc 933 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); dcrtc 934 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->spu_iopad_ctrl, dcrtc 935 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_IOPAD_CONTROL); dcrtc 936 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); dcrtc 939 drivers/gpu/drm/armada/armada_crtc.c CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); dcrtc 940 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); dcrtc 941 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); dcrtc 942 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); dcrtc 943 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); dcrtc 946 drivers/gpu/drm/armada/armada_crtc.c dcrtc); dcrtc 950 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->variant->init) { dcrtc 951 drivers/gpu/drm/armada/armada_crtc.c ret = dcrtc->variant->init(dcrtc, dev); dcrtc 957 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); dcrtc 959 drivers/gpu/drm/armada/armada_crtc.c priv->dcrtc[dcrtc->num] = dcrtc; dcrtc 961 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.port = port; dcrtc 975 drivers/gpu/drm/armada/armada_crtc.c ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL, dcrtc 980 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); dcrtc 982 drivers/gpu/drm/armada/armada_crtc.c ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256); dcrtc 986 drivers/gpu/drm/armada/armada_crtc.c drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256); dcrtc 988 drivers/gpu/drm/armada/armada_crtc.c return armada_overlay_plane_create(drm, 1 << dcrtc->num); dcrtc 993 drivers/gpu/drm/armada/armada_crtc.c kfree(dcrtc); dcrtc 1046 drivers/gpu/drm/armada/armada_crtc.c struct armada_crtc *dcrtc = dev_get_drvdata(dev); dcrtc 1048 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_destroy(&dcrtc->crtc); dcrtc 88 drivers/gpu/drm/armada/armada_crtc.h int armada_crtc_select_clock(struct armada_crtc *dcrtc, dcrtc 34 drivers/gpu/drm/armada/armada_debugfs.c struct armada_crtc *dcrtc = m->private; dcrtc 38 drivers/gpu/drm/armada/armada_debugfs.c u32 v = readl_relaxed(dcrtc->base + i); dcrtc 54 drivers/gpu/drm/armada/armada_debugfs.c struct armada_crtc *dcrtc; dcrtc 76 drivers/gpu/drm/armada/armada_debugfs.c dcrtc = ((struct seq_file *)file->private_data)->private; dcrtc 77 drivers/gpu/drm/armada/armada_debugfs.c v = readl(dcrtc->base + reg); dcrtc 80 drivers/gpu/drm/armada/armada_debugfs.c writel(v, dcrtc->base + reg); dcrtc 94 drivers/gpu/drm/armada/armada_debugfs.c void armada_drm_crtc_debugfs_init(struct armada_crtc *dcrtc) dcrtc 96 drivers/gpu/drm/armada/armada_debugfs.c debugfs_create_file("armada-regs", 0600, dcrtc->crtc.debugfs_entry, dcrtc 97 drivers/gpu/drm/armada/armada_debugfs.c dcrtc, &armada_debugfs_crtc_reg_fops); dcrtc 59 drivers/gpu/drm/armada/armada_drm.h struct armada_crtc *dcrtc[2]; dcrtc 81 drivers/gpu/drm/armada/armada_drm.h void armada_drm_crtc_debugfs_init(struct armada_crtc *dcrtc); dcrtc 72 drivers/gpu/drm/armada/armada_overlay.c struct armada_crtc *dcrtc; dcrtc 88 drivers/gpu/drm/armada/armada_overlay.c dcrtc = drm_to_armada_crtc(state->crtc); dcrtc 89 drivers/gpu/drm/armada/armada_overlay.c regs = dcrtc->regs + dcrtc->regs_idx; dcrtc 207 drivers/gpu/drm/armada/armada_overlay.c dcrtc->variant->has_spu_adv_reg) dcrtc 211 drivers/gpu/drm/armada/armada_overlay.c dcrtc->regs_idx += idx; dcrtc 217 drivers/gpu/drm/armada/armada_overlay.c struct armada_crtc *dcrtc; dcrtc 231 drivers/gpu/drm/armada/armada_overlay.c dcrtc = drm_to_armada_crtc(old_state->crtc); dcrtc 232 drivers/gpu/drm/armada/armada_overlay.c regs = dcrtc->regs + dcrtc->regs_idx; dcrtc 239 drivers/gpu/drm/armada/armada_overlay.c dcrtc->regs_idx += idx; dcrtc 162 drivers/gpu/drm/armada/armada_plane.c struct armada_crtc *dcrtc; dcrtc 178 drivers/gpu/drm/armada/armada_plane.c dcrtc = drm_to_armada_crtc(state->crtc); dcrtc 179 drivers/gpu/drm/armada/armada_plane.c regs = dcrtc->regs + dcrtc->regs_idx; dcrtc 241 drivers/gpu/drm/armada/armada_plane.c dcrtc->regs_idx += idx; dcrtc 247 drivers/gpu/drm/armada/armada_plane.c struct armada_crtc *dcrtc; dcrtc 261 drivers/gpu/drm/armada/armada_plane.c dcrtc = drm_to_armada_crtc(old_state->crtc); dcrtc 262 drivers/gpu/drm/armada/armada_plane.c regs = dcrtc->regs + dcrtc->regs_idx; dcrtc 270 drivers/gpu/drm/armada/armada_plane.c dcrtc->regs_idx += idx;