dcrbase_isram      77 arch/powerpc/platforms/4xx/soc.c 	u32 dcrbase_isram;
dcrbase_isram     102 arch/powerpc/platforms/4xx/soc.c 	dcrbase_isram = dcrreg[0];
dcrbase_isram     125 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
dcrbase_isram     126 arch/powerpc/platforms/4xx/soc.c 	      mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
dcrbase_isram     127 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
dcrbase_isram     128 arch/powerpc/platforms/4xx/soc.c 	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
dcrbase_isram     129 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
dcrbase_isram     130 arch/powerpc/platforms/4xx/soc.c 	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
dcrbase_isram     131 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
dcrbase_isram     132 arch/powerpc/platforms/4xx/soc.c 	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
dcrbase_isram     133 arch/powerpc/platforms/4xx/soc.c 	mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
dcrbase_isram     134 arch/powerpc/platforms/4xx/soc.c 	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);