DP_VID_TIMING 330 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); DP_VID_TIMING 334 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); DP_VID_TIMING 993 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); DP_VID_TIMING 1003 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); DP_VID_TIMING 92 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SRI(DP_VID_TIMING, DP, id), \ DP_VID_TIMING 165 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ DP_VID_TIMING 316 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) DP_VID_TIMING 666 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_TIMING; DP_VID_TIMING 958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); DP_VID_TIMING 968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE_2(DP_VID_TIMING, DP_VID_TIMING 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SRI(DP_VID_TIMING, DP, id), \ DP_VID_TIMING 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_VID_TIMING; DP_VID_TIMING 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); DP_VID_TIMING 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(DP_VID_TIMING,