DP_VID_STREAM_CNTL  421 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
DP_VID_STREAM_CNTL   68 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
DP_VID_STREAM_CNTL  149 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DP_VID_STREAM_CNTL;
DP_VID_STREAM_CNTL  933 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
DP_VID_STREAM_CNTL  939 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
DP_VID_STREAM_CNTL  947 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
DP_VID_STREAM_CNTL  954 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
DP_VID_STREAM_CNTL 1027 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
DP_VID_STREAM_CNTL   91 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
DP_VID_STREAM_CNTL  161 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
DP_VID_STREAM_CNTL  162 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
DP_VID_STREAM_CNTL  163 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
DP_VID_STREAM_CNTL  665 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_VID_STREAM_CNTL;
DP_VID_STREAM_CNTL  392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
DP_VID_STREAM_CNTL   61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
DP_VID_STREAM_CNTL  103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DP_VID_STREAM_CNTL;
DP_VID_STREAM_CNTL  892 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
DP_VID_STREAM_CNTL  899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
DP_VID_STREAM_CNTL  907 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
DP_VID_STREAM_CNTL  914 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
DP_VID_STREAM_CNTL  994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
DP_VID_STREAM_CNTL   89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
DP_VID_STREAM_CNTL  134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_VID_STREAM_CNTL;
DP_VID_STREAM_CNTL  496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
DP_VID_STREAM_CNTL  497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
DP_VID_STREAM_CNTL  528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);