dco_khz          2703 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
dco_khz          2714 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
dco_khz          2721 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	m2div_int = dco_khz / (refclk_khz * m1div);
dco_khz          2724 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		m2div_int = dco_khz / (refclk_khz * m1div);
dco_khz          2731 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	m2div_rem = dco_khz % (refclk_khz * m1div);
dco_khz          2781 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
dco_khz          2783 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (dco_khz >= 9000000) {
dco_khz          2792 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		tmp = mul_u32_u32(dco_khz, 47 * 32);
dco_khz          2796 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		tmp = mul_u32_u32(dco_khz, 1000);