dco_freq 1277 drivers/gpu/drm/i915/display/intel_ddi.c u32 p0, p1, p2, dco_freq; dco_freq 1318 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) dco_freq 1321 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) dco_freq 1327 drivers/gpu/drm/i915/display/intel_ddi.c return dco_freq / (p0 * p1 * p2 * 5); dco_freq 1333 drivers/gpu/drm/i915/display/intel_ddi.c u32 p0, p1, p2, dco_freq, ref_clock; dco_freq 1374 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) dco_freq 1377 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> dco_freq 1383 drivers/gpu/drm/i915/display/intel_ddi.c return dco_freq / (p0 * p1 * p2 * 5); dco_freq 1118 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u64 dco_freq; /* chosen dco freq */ dco_freq 1135 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u64 dco_freq, dco_freq 1140 drivers/gpu/drm/i915/display/intel_dpll_mgr.c deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), dco_freq 1144 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dco_freq >= central_freq) { dco_freq 1149 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctx->dco_freq = dco_freq; dco_freq 1157 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctx->dco_freq = dco_freq; dco_freq 1226 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u64 dco_freq; dco_freq 1276 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco_freq = p0 * p1 * p2 * afe_clock; dco_freq 1282 drivers/gpu/drm/i915/display/intel_dpll_mgr.c params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); dco_freq 1284 drivers/gpu/drm/i915/display/intel_dpll_mgr.c div_u64((div_u64(dco_freq, 24) - dco_freq 1319 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u64 dco_freq = p * afe_clock; dco_freq 1323 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco_freq, dco_freq 2210 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 dco_freq, u32 ref_freq, dco_freq 2251 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco = div_u64((u64)dco_freq << 15, ref_freq);