dco 106 drivers/clk/ti/adpll.c #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco) dco 179 drivers/clk/ti/adpll.c struct ti_adpll_dco_data dco; dco 422 drivers/clk/ti/adpll.c struct ti_adpll_dco_data *dco = to_dco(hw); dco 423 drivers/clk/ti/adpll.c struct ti_adpll_data *d = to_adpll(dco); dco 433 drivers/clk/ti/adpll.c struct ti_adpll_dco_data *dco = to_dco(hw); dco 434 drivers/clk/ti/adpll.c struct ti_adpll_data *d = to_adpll(dco); dco 441 drivers/clk/ti/adpll.c struct ti_adpll_dco_data *dco = to_dco(hw); dco 442 drivers/clk/ti/adpll.c struct ti_adpll_data *d = to_adpll(dco); dco 454 drivers/clk/ti/adpll.c struct ti_adpll_dco_data *dco = to_dco(hw); dco 455 drivers/clk/ti/adpll.c struct ti_adpll_data *d = to_adpll(dco); dco 525 drivers/clk/ti/adpll.c d->dco.hw.init = &init; dco 540 drivers/clk/ti/adpll.c clock = devm_clk_register(d->dev, &d->dco.hw); dco 247 drivers/clk/ti/dpll3xxx.c static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) dco 255 drivers/clk/ti/dpll3xxx.c *dco = 2; dco 257 drivers/clk/ti/dpll3xxx.c *dco = 4; dco 305 drivers/clk/ti/dpll3xxx.c u8 dco, sd_div, ai = 0; dco 340 drivers/clk/ti/dpll3xxx.c _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); dco 342 drivers/clk/ti/dpll3xxx.c v |= dco << __ffs(dd->dco_mask); dco 1310 drivers/gpu/drm/i915/display/intel_dpll_mgr.c unsigned int dco, d, i; dco 1316 drivers/gpu/drm/i915/display/intel_dpll_mgr.c for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { dco 1322 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco_central_freq[dco], dco 2213 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 dco; dco 2251 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco = div_u64((u64)dco_freq << 15, ref_freq); dco 2253 drivers/gpu/drm/i915/display/intel_dpll_mgr.c params->dco_integer = dco >> 15; dco 2254 drivers/gpu/drm/i915/display/intel_dpll_mgr.c params->dco_fraction = dco & 0x7fff; dco 2287 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 dco, best_dco = 0, dco_centrality = 0; dco 2292 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco = afe_clock * dividers[d]; dco 2294 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if ((dco <= dco_max) && (dco >= dco_min)) { dco 2295 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dco_centrality = abs(dco - dco_mid); dco 2300 drivers/gpu/drm/i915/display/intel_dpll_mgr.c best_dco = dco; dco 2639 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int dco = div1 * div2 * clock_khz * 5; dco 2643 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dco < dco_min_freq || dco > dco_max_freq) dco 2673 drivers/gpu/drm/i915/display/intel_dpll_mgr.c *target_dco_khz = dco; dco 1580 drivers/media/dvb-frontends/drx39xyj/drx_driver.h s32 dco; /* frequency adjustment (A) */ dco 231 drivers/media/pci/cobalt/cobalt-cpld.c u64 dco; dco 246 drivers/media/pci/cobalt/cobalt-cpld.c dco = (u64)f_out * mult; dco 247 drivers/media/pci/cobalt/cobalt-cpld.c if (dco < DCO_MIN || dco > DCO_MAX) dco 249 drivers/media/pci/cobalt/cobalt-cpld.c div_u64_rem((dco << 28) + f_xtal / 2, f_xtal, &d); dco 258 drivers/media/pci/cobalt/cobalt-cpld.c dco = (u64)f_out * multipliers[i_best].mult; dco 261 drivers/media/pci/cobalt/cobalt-cpld.c rfreq = div_u64(dco << 28, f_xtal); dco 313 drivers/net/wireless/ti/wlcore/acx.c struct acx_dco_itrim_params *dco; dco 319 drivers/net/wireless/ti/wlcore/acx.c dco = kzalloc(sizeof(*dco), GFP_KERNEL); dco 320 drivers/net/wireless/ti/wlcore/acx.c if (!dco) { dco 325 drivers/net/wireless/ti/wlcore/acx.c dco->enable = c->enable; dco 326 drivers/net/wireless/ti/wlcore/acx.c dco->timeout = cpu_to_le32(c->timeout); dco 329 drivers/net/wireless/ti/wlcore/acx.c dco, sizeof(*dco)); dco 336 drivers/net/wireless/ti/wlcore/acx.c kfree(dco);