dcn2_1_soc 159 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { dcn2_1_soc 1282 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.num_chans = bw_params->num_channels; dcn2_1_soc 1283 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.num_states = 0; dcn2_1_soc 1287 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.clock_limits[i].state = i; dcn2_1_soc 1288 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; dcn2_1_soc 1289 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; dcn2_1_soc 1290 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; dcn2_1_soc 1292 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; dcn2_1_soc 1293 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.num_states++; dcn2_1_soc 1539 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);