DP_SEC_TIMESTAMP 1613 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
DP_SEC_TIMESTAMP 1454 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
DP_SEC_TIMESTAMP   94 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_SEC_TIMESTAMP, DP, id)
DP_SEC_TIMESTAMP  197 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
DP_SEC_TIMESTAMP  668 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_TIMESTAMP;
DP_SEC_TIMESTAMP 1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
DP_SEC_TIMESTAMP   92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_TIMESTAMP, DP, id), \
DP_SEC_TIMESTAMP  137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_SEC_TIMESTAMP;