DP_SEC_STREAM_ENABLE 1620 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 890 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 908 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c DP_SEC_STREAM_ENABLE, 0); DP_SEC_STREAM_ENABLE 916 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 1512 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 1527 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c DP_SEC_STREAM_ENABLE, 0); DP_SEC_STREAM_ENABLE 1533 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 155 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ DP_SEC_STREAM_ENABLE 238 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ DP_SEC_STREAM_ENABLE 429 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint8_t DP_SEC_STREAM_ENABLE; DP_SEC_STREAM_ENABLE 560 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_STREAM_ENABLE; DP_SEC_STREAM_ENABLE 753 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 867 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c DP_SEC_STREAM_ENABLE, 0); DP_SEC_STREAM_ENABLE 874 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 1451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 1466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c DP_SEC_STREAM_ENABLE, 0); DP_SEC_STREAM_ENABLE 1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ DP_SEC_STREAM_ENABLE 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h type DP_SEC_STREAM_ENABLE;\ DP_SEC_STREAM_ENABLE 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c DP_SEC_STREAM_ENABLE, 1); DP_SEC_STREAM_ENABLE 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); DP_SEC_STREAM_ENABLE 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);